MC68030 MMU and On-Chip Caches

The MC68030 — the CPU in the Amiga 3000 and Amiga 4000 — is a significant evolution of the 68020. Its two headline features are an on-chip Memory Management Unit (MMU) providing demand-paged virtual memory, and split Harvard-architecture caches (instruction + data). This article documents the hardware from the MC68030 User's Manual (Motorola, 3rd ed., 1987).

MMU overview

The 68030 MMU translates logical (virtual) addresses to physical addresses using multi-level translation tables stored in memory. It caches recent translations in a 22-entry fully associative Address Translation Cache (ATC) — the MC68030's TLB. When the ATC contains the mapping for a bus cycle, no table search is needed.

Key features: - Multiple-level translation tables with short- and long-format descriptors - Table searches performed automatically in microcode (no software handler needed for misses) - 22-entry fully associative ATC (vs. the 68851's 64 entries) - Eight page sizes: 256 bytes to 32K bytes - Two transparent translation blocks (TT0/TT1) — pass-through ranges that bypass table walks - Separate user and supervisor root pointers - Write protection and supervisor protection per page - Used and Modified bits automatically maintained in tables and ATC - Cache inhibit output (CLOUT) asserted on a per-page basis - 32-bit logical and physical addresses - Translation can be disabled in software or via external MMUDIS signal

MMU registers

All are supervisor-only, accessed via PMOVE:

Register Width Purpose
CRP (CPU Root Pointer) 64-bit Points to root of translation table tree for current task (user space, or both if SRP disabled)
SRP (Supervisor Root Pointer) 64-bit Points to root of supervisor translation tree (used only when SRE bit in TC is set)
TC (Translation Control) 32-bit Enables/disables translation, enables SRP, selects page size
TT0, TT1 (Transparent Translation) 32-bit each Define pass-through address ranges that bypass the MMU
MMUSR (MMU Status Register) 16-bit Status from PTEST — resident/modified/superuser bits, ATC hit/miss

When a new task begins execution, the OS writes a new root pointer to the CRP and optionally flushes the ATC (since cached entries may belong to the previous task's address space).

MMU instructions

Instruction Description
PFLUSH Flush specific entry(ies) from the ATC
PFLUSHA Flush all entries from the ATC
PLOAD Load an entry into the ATC
PMOVE Move data to/from MMU registers (CRP, SRP, TC, TT0, TT1, MMUSR)
PTESTR Test read access — translates an address and updates MMUSR with ATC result
PTESTW Test write access — same as PTESTR but for write permission

Address translation

The MMU uses a tree of translation tables:

  1. CRP (or SRP for supervisor mode) points to the root table
  2. High-order logical address bits index into the root table → table descriptor (points to next level)
  3. Mid-order bits index into the next table → another table descriptor or a page descriptor
  4. Low-order bits select the offset within the page

Page sizes are programmable via TC register: 256B, 512B, 1KB, 2KB, 4KB, 8KB, 16KB, or 32KB.

Descriptor types: page descriptors (final mapping), table descriptors (point to next level), early-termination descriptors (short-format — stop before the last level), and invalid descriptors (trigger page fault).

Transparent translation (TT0/TT1)

Two independent registers define address ranges that bypass the MMU entirely — accesses matching a TT register go straight to physical memory without table lookup or ATC caching. This is essential for: - Framebuffer/video memory (which doesn't need translation) - I/O space - Boot ROM (before the MMU tables are set up)

Each TT register matches on function code (user/supervisor, data/program) and address range (programmable base and mask).

Split on-chip caches

Unlike the 68020's instruction-only cache, the 68030 has two independent 256-byte caches:

Cache Size Organization
Instruction cache 256 bytes 16 entries × 16 bytes (4 longwords)
Data cache 256 bytes 16 entries × 16 bytes (4 longwords)

Both caches support burst fill — during burst-mode bus accesses, an entire 16-byte entry is filled in four consecutive longword transfers (2-1-1-1 or 3-1-1-1 access patterns).

The CACR (Cache Address Control Register) independently controls each cache: enable, freeze, clear, and clear-entry bits for instruction and data caches separately.

The data cache uses write allocation — on a write miss, the processor allocates a cache entry and writes to it, also writing through to memory (write-through policy). This extends caching benefits to all memory accesses, not just instruction fetches.

Bus enhancements

The 68030 adds a synchronous bus mode via the STERM signal. When a memory system can respond within one clock cycle (e.g., fast SRAM with burst support), the processor asserts STERM instead of DSACKx, enabling: - Single-cycle bus accesses - Burst cycles: 4 longwords in 4 consecutive clock cycles (vs. 4 separate asynchronous cycles) - External CBREQ/CBACK handshake for burst support

The STATUS and REFILL pins expose internal microsequencer state and pipeline refills for real-time in-circuit emulation and debugging.

MC68030 vs MC68851 differences

The 68030's on-chip MMU is a subset of the external MC68851 PMMU (used with the 68020). The MC68851 features NOT available on the 68030:

  • Access levels
  • Breakpoint registers
  • Root pointer table
  • Aliases for tasks
  • Lockable ATC entries
  • Globally shared ATC entries
  • 64-entry ATC (vs. 22-entry)

The 68030 is generally program-compatible with the 68020/MC68851 combination, but the following MC68851 instructions must be emulated or avoided: PVALID, PFLUSHR, PFLUSHS, PBcc, PDBcc, PScc, PTRAPcc, PSAVE, PRESTORE.

Relevance to the Amiga

Amiga CPU MMU use
A3000 MC68030 (16/25 MHz) Enforcer uses the MMU for memory trap detection
A4000 MC68030 (25 MHz) Same; also used for virtual memory if enabled
A4000/040 MC68040 (25 MHz) 68040 has dual demand-paged MMUs (see MC68040 and MC68060 Architecture)

The 68030's MMU is the hardware basis for Enforcer (the memory-access debugger documented in Amiga Debugging Tools) and for mmu.library on OS 3.2.

See Also

Sources: Motorola, Inc., "MC68030 Enhanced 32-Bit Microprocessor User's Manual" 3rd Edition (1987), Chapters 1, 6, 7, 9. Raw: raw/hardware/mc68030um.md Updated: 2026-08-09