Amiga Custom Chip Register Reference¶

Complete hardware register map for all three Amiga chip generations — OCS (Original Chip Set, 1985), ECS (Enhanced Chip Set, 1988–1990), and AGA (Advanced Graphics Architecture, 1992–1994). Sources: the OCS/ECS register table from the Amiga Hardware Reference Manual (Commodore-Amiga, 1992), the AGA additions from the AA chip set feature summary, and the per-register descriptions from the amiga-dev.wikidot.com community wiki (hardware:<NAME> pages, accessed 2026).

Detailed register descriptions¶

Click on any register name in the table above to jump to the corresponding detailed description. Registers that share the same hardware definition are documented together, with an anchor for every individual register name. The descriptions are aligned with the per-register pages linked from the amiga-dev hardware reference.

Register addresses are shown as offsets from $DFF000 for custom chips and $BFE000/$BFD000 for CIA chips. All custom-chip registers are 16-bit unless noted. Access modes: R = read-only, W = write-only, ER = early read (dummy), RW = read/write, S = strobe.

Note: The addresses shown here are used by the special custom chips (Paula, Agnus/Alice, and Denise/Lisa) for transferring data among themselves. The Copper uses these addresses for writing to the special chip registers.

OCS / ECS / AGA Custom Chip Registers¶

Address	Name	Access	OCS	ECS	AGA	Description
$DFF000	BLTDDAT	ER	●	●	●	Blitter dest. early read (dummy address)
$DFF002	DMACONR	R	●	●	●	Dma control (and blitter status) read
$DFF004	VPOSR	R	●	●	●	Read vertical most sig. bits (and frame flop)
$DFF006	VHPOSR	R	●	●	●	Read vert and horiz position of beam
$DFF008	DSKDATR	ER	●	●	●	Disk data early read (dummy address)
$DFF00A	JOY0DAT	R	●	●	●	Joystick-mouse 0 data (vert, horiz)
$DFF00C	JOY1DAT	R	●	●	●	Joystick-mouse 1 data (vert, horiz)
$DFF00E	CLXDAT	R	●	●	●	Collision data reg. (read and clear)
$DFF010	ADKCONR	R	●	●	●	Audio,disk control register read
$DFF012	POT0DAT	R	●	●	●	Pot counter data left pair (vert, horiz)
$DFF014	POT1DAT	R	●	●	●	Pot counter data right pair (vert, horiz)
$DFF016	POTINP	R	●	●	●	Pot pin data read
$DFF018	SERDATR	R	●	●	●	Serial port data and status read
$DFF01A	DSKBYTR	R	●	●	●	Disk data byte and status read
$DFF01C	INTENAR	R	●	●	●	Interrupt enable bits read
$DFF01E	INTREQR	R	●	●	●	Interrupt request bits read
$DFF020	DSKPTH	W	●	●	●	Disk pointer (high 5 bits, was 3 bits)
$DFF022	DSKPTL	W	●	●	●	Disk pointer (low 15 bits)
$DFF024	DSKLEN	W	●	●	●	Disk length
$DFF026	DSKDAT	W	●	●	●	Disk DMA data write
$DFF028	REFPTR	W	●	●	●	Refresh pointer
$DFF02A	VPOSW	W	●	●	●	Write vert most sig. bits (and frame flop)
$DFF02C	VHPOSW	W	●	●	●	Write vert and horiz pos of beam
$DFF02E	COPCON	W	●	●	●	Coprocessor control
$DFF030	SERDAT	W	●	●	●	Serial port data and stop bits write
$DFF032	SERPER	W	●	●	●	Serial port period and control
$DFF034	POTGO	W	●	●	●	Pot count start,pot pin drive enable data
$DFF036	JOYTEST	W	●	●	●	Write to all 4 joystick-mouse counters at once
$DFF038	STREQU	S	●	●	●	Strobe for horiz sync with VB and EQU
$DFF03A	STRVBL	S	●	●	●	Strobe for horiz sync with VB (vert blank)
$DFF03C	STRHOR	S	●	●	●	Strobe for horiz sync
$DFF03E	STRLONG	S	●	●	●	Strobe for identification of long horiz line
$DFF040	BLTCON0	W	●	●	●	Blitter control register 0
$DFF042	BLTCON1	W	●	●	●	Blitter control register 1
$DFF044	BLTAFWM	W	●	●	●	Blitter first word mask for source A
$DFF046	BLTALWM	W	●	●	●	Blitter last word mask for source A
$DFF048	BLTCPTH	W	●	●	●	Blitter pointer to source C (high 5 bits, was 3 bits)
$DFF04A	BLTCPTL	W	●	●	●	Blitter pointer to source C (low 15 bits)
$DFF04C	BLTBPTH	W	●	●	●	Blitter pointer to source B (high 5 bits, was 3 bits)
$DFF04E	BLTBPTL	W	●	●	●	Blitter pointer to source B (low 15 bits)
$DFF050	BLTAPTH	W	●	●	●	Blitter pointer to source A (high 5 bits, was 3 bits)
$DFF052	BLTAPTL	W	●	●	●	Blitter pointer to source A (low 15 bits)
$DFF054	BLTDPTH	W	●	●	●	Blitter pointer to dest D (high 5 bits, was 3 bits)
$DFF056	BLTDPTL	W	●	●	●	Blitter pointer to dest D (low 15 bits)
$DFF058	BLTSIZE	W	●	●	●	Blitter start and size (win/width,height)
$DFF05A	BLTCON0L	W		●	●	Blitter control 0, lower 8 bits (minterms)
$DFF05C	BLTSIZV	W		●	●	Blitter V size (for 15 bit vertical size)
$DFF05E	BLTSIZH	W		●	●	Blitter H size and start (for 11 bit H size)
$DFF060	BLTCMOD	W	●	●	●	Blitter modulo for source C
$DFF062	BLTBMOD	W	●	●	●	Blitter modulo for source B
$DFF064	BLTAMOD	W	●	●	●	Blitter modulo for source A
$DFF066	BLTDMOD	W	●	●	●	Blitter modulo for dest D
$DFF070	BLTCDAT	W	●	●	●	Blitter source C data register
$DFF072	BLTBDAT	W	●	●	●	Blitter source B data register
$DFF074	BLTADAT	W	●	●	●	Blitter source A data register
$DFF078	SPRHDAT	W		●	●	Ext. logic UHRES sprite pointer and data identifier
$DFF07A	BPLHDAT	W		●	●	Ext. logic UHRES bit plane identifier
$DFF07C	DENISEID	R		●	●	Chip revision level for Denise/Lisa (video out chip)
$DFF07E	DSKSYNC	W	●	●	●	Disk sync pattern reg for disk read
$DFF080	COP1LCH	W	●	●	●	Coprocessor 1st location (high 5 bits,was 3 bits)
$DFF082	COP1LCL	W	●	●	●	Coprocessor 1st location (low 15 bits)
$DFF084	COP2LCH	W	●	●	●	Coprocessor 2nd location(high 5 bits,was 3 bits)
$DFF086	COP2LCL	W	●	●	●	Coprocessor 2nd location (low 15 bits)
$DFF088	COPJMP1	S	●	●	●	Coprocessor restart at 1st location
$DFF08A	COPJMP2	S	●	●	●	Coprocessor restart at 2nd location
$DFF08C	COPINS	S	●	●	●	Coprocessor inst fetch identify
$DFF08E	DIWSTRT	W	●	●	●	Display window start (upper left vert,horiz pos)
$DFF090	DIWSTOP	W	●	●	●	Display window stop (lower right vert,horiz pos)
$DFF092	DDFSTRT	W	●	●	●	Display bit plane data fetch start,horiz pos
$DFF094	DDFSTOP	W	●	●	●	Display bit plane data fetch stop,horiz pos
$DFF096	DMACON	W	●	●	●	DMA control write (clear or set)
$DFF098	CLXCON	W	●	●	●	Collision control
$DFF09A	INTENA	W	●	●	●	Interrupt enable bits (clear or set bits)
$DFF09C	INTREQ	W	●	●	●	Interrupt request bits (clear or set bits)
$DFF09E	ADKCON	W	●	●	●	Audio,disk,UART control
$DFF0A0	AUD0LCH	W	●	●	●	Audio channel 0 location (high 5 bits was 3 bits)
$DFF0A2	AUD0LCL	W	●	●	●	Audio channel 0 location (low 15 bits)
$DFF0A4	AUD0LEN	W	●	●	●	Audio channel 0 length
$DFF0A6	AUD0PER	W	●	●	●	Audio channel 0 period
$DFF0A8	AUD0VOL	W	●	●	●	Audio channel 0 volume
$DFF0AA	AUD0DAT	W	●	●	●	Audio channel 0 data
$DFF0B0	AUD1LCH	W	●	●	●	Audio channel 1 location (high 5 bits was 3 bits)
$DFF0B2	AUD1LCL	W	●	●	●	Audio channel 1 location (low 15 bits)
$DFF0B4	AUD1LEN	W	●	●	●	Audio channel 1 length
$DFF0B6	AUD1PER	W	●	●	●	Audio channel 1 period
$DFF0B8	AUD1VOL	W	●	●	●	Audio channel 1 volume
$DFF0BA	AUD1DAT	W	●	●	●	Audio channel 1 data
$DFF0C0	AUD2LCH	W	●	●	●	Audio channel 2 location (high 5 bits was 3 bits)
$DFF0C2	AUD2LCL	W	●	●	●	Audio channel 2 location (low 15 bits)
$DFF0C4	AUD2LEN	W	●	●	●	Audio channel 2 length
$DFF0C6	AUD2PER	W	●	●	●	Audio channel 2 period
$DFF0C8	AUD2VOL	W	●	●	●	Audio channel 2 volume
$DFF0CA	AUD2DAT	W	●	●	●	Audio channel 2 data
$DFF0D0	AUD3LCH	W	●	●	●	Audio channel 3 location (high 5 bits was 3 bits)
$DFF0D2	AUD3LCL	W	●	●	●	Audio channel 3 location (low 15 bits)
$DFF0D4	AUD3LEN	W	●	●	●	Audio channel 3 length
$DFF0D6	AUD3PER	W	●	●	●	Audio channel 3 period
$DFF0D8	AUD3VOL	W	●	●	●	Audio channel 3 volume
$DFF0DA	AUD3DAT	W	●	●	●	Audio channel 3 data
$DFF0E0	BPL1PTH	W	●	●	●	Bitplane pointer 1 (high 5 bits was 3 bits)
$DFF0E2	BPL1PTL	W	●	●	●	Bitplane pointer 1 (low 15 bits)
$DFF0E4	BPL2PTH	W	●	●	●	Bitplane pointer 2 (high 5 bits was 3 bits)
$DFF0E6	BPL2PTL	W	●	●	●	Bitplane pointer 2 (low 15 bits)
$DFF0E8	BPL3PTH	W	●	●	●	Bitplane pointer 3 (high 5 bits was 3 bits)
$DFF0EA	BPL3PTL	W	●	●	●	Bitplane pointer 3 (low 15 bits)
$DFF0EC	BPL4PTH	W	●	●	●	Bitplane pointer 4 (high 5 bits was 3 bits)
$DFF0EE	BPL4PTL	W	●	●	●	Bitplane pointer 4 (low 15 bits)
$DFF0F0	BPL5PTH	W	●	●	●	Bitplane pointer 5 (high 5 bits was 3 bits)
$DFF0F2	BPL5PTL	W	●	●	●	Bitplane pointer 5 (low 15 bits)
$DFF0F4	BPL6PTH	W	●	●	●	Bitplane pointer 6 (high 5 bits was 3 bits)
$DFF0F6	BPL6PTL	W	●	●	●	Bitplane pointer 6 (low 15 bits)
$DFF0F8	BPL7PTH	W			●	Bitplane pointer 7 (high 5 bits was 3 bits)
$DFF0FA	BPL7PTL	W			●	Bitplane pointer 7 (low 15 bits)
$DFF0FC	BPL8PTH	W			●	Bitplane pointer 8 (high 5 bits was 3 bits)
$DFF0FE	BPL8PTL	W			●	Bitplane pointer 8 (low 15 bits)
$DFF100	BPLCON0	W	●	●	●	Bitplane control (miscellaneous control bits)
$DFF102	BPLCON1	W	●	●	●	Bitplane control (scroll value)
$DFF104	BPLCON2	W	●	●	●	Bitplane control (video priority control)
$DFF106	BPLCON3	W		●	●	Bitplane control (enhanced features)
$DFF108	BPL1MOD	W	●	●	●	Bitplane modulo (odd planes)
$DFF10A	BPL2MOD	W	●	●	●	Bitplane modulo (even planes)
$DFF10C	BPLCON4	W			●	Bitplane control (bitplane and sprite-masks)
$DFF10E	CLXCON2	W			●	Extended collision control
$DFF110	BPL1DAT	W	●	●	●	Bitplane 1 data (parallel to serial convert)
$DFF112	BPL2DAT	W	●	●	●	Bitplane 2 data (parallel to serial convert)
$DFF114	BPL3DAT	W	●	●	●	Bitplane 3 data (parallel to serial convert)
$DFF116	BPL4DAT	W	●	●	●	Bitplane 4 data (parallel to serial convert)
$DFF118	BPL5DAT	W	●	●	●	Bitplane 5 data (parallel to serial convert)
$DFF11A	BPL6DAT	W	●	●	●	Bitplane 6 data (parallel to serial convert)
$DFF11C	BPL7DAT	W			●	Bitplane 7 data (parallel to serial convert)
$DFF11E	BPL8DAT	W			●	Bitplane 8 data (parallel to serial convert)
$DFF120	SPR0PTH	W	●	●	●	Sprite 0 pointer (high 5 bits was 3 bits)
$DFF122	SPR0PTL	W	●	●	●	Sprite 0 pointer (low 15 bits)
$DFF124	SPR1PTH	W	●	●	●	Sprite 1 pointer (high 5 bits was 3 bits)
$DFF126	SPR1PTL	W	●	●	●	Sprite 1 pointer (low 15 bits)
$DFF128	SPR2PTH	W	●	●	●	Sprite 2 pointer (high 5 bits was 3 bits)
$DFF12A	SPR2PTL	W	●	●	●	Sprite 2 pointer (low 15 bits)
$DFF12C	SPR3PTH	W	●	●	●	Sprite 3 pointer (high 5 bits was 3 bits)
$DFF12E	SPR3PTL	W	●	●	●	Sprite 3 pointer (low 15 bits)
$DFF130	SPR4PTH	W	●	●	●	Sprite 4 pointer (high 5 bits was 3 bits)
$DFF132	SPR4PTL	W	●	●	●	Sprite 4 pointer (low 15 bits)
$DFF134	SPR5PTH	W	●	●	●	Sprite 5 pointer (high 5 bits was 3 bits)
$DFF136	SPR5PTL	W	●	●	●	Sprite 5 pointer (low 15 bits)
$DFF138	SPR6PTH	W	●	●	●	Sprite 6 pointer (high 5 bits was 3 bits)
$DFF13A	SPR6PTL	W	●	●	●	Sprite 6 pointer (low 15 bits)
$DFF13C	SPR7PTH	W	●	●	●	Sprite 7 pointer (high 5 bits was 3 bits)
$DFF13E	SPR7PTL	W	●	●	●	Sprite 7 pointer (low 15 bits)
$DFF140	SPR0POS	W	●	●	●	Sprite 0 vert,horiz start pos data
$DFF142	SPR0CTL	W	●	●	●	Sprite 0 position and control data
$DFF144	SPR0DATA	W	●	●	●	Sprite 0 image data register A
$DFF146	SPR0DATB	W	●	●	●	Sprite 0 image data register B
$DFF148	SPR1POS	W	●	●	●	Sprite 1 vert,horiz start pos data
$DFF14A	SPR1CTL	W	●	●	●	Sprite 1 position and control data
$DFF14C	SPR1DATA	W	●	●	●	Sprite 1 image data register A
$DFF14E	SPR1DATB	W	●	●	●	Sprite 1 image data register B
$DFF150	SPR2POS	W	●	●	●	Sprite 2 vert,horiz start pos data
$DFF152	SPR2CTL	W	●	●	●	Sprite 2 position and control data
$DFF154	SPR2DATA	W	●	●	●	Sprite 2 image data register A
$DFF156	SPR2DATB	W	●	●	●	Sprite 2 image data register B
$DFF158	SPR3POS	W	●	●	●	Sprite 3 vert,horiz start pos data
$DFF15A	SPR3CTL	W	●	●	●	Sprite 3 position and control data
$DFF15C	SPR3DATA	W	●	●	●	Sprite 3 image data register A
$DFF15E	SPR3DATB	W	●	●	●	Sprite 3 image data register B
$DFF160	SPR4POS	W	●	●	●	Sprite 4 vert,horiz start pos data
$DFF162	SPR4CTL	W	●	●	●	Sprite 4 position and control data
$DFF164	SPR4DATA	W	●	●	●	Sprite 4 image data register A
$DFF166	SPR4DATB	W	●	●	●	Sprite 4 image data register B
$DFF168	SPR5POS	W	●	●	●	Sprite 5 vert,horiz start pos data
$DFF16A	SPR5CTL	W	●	●	●	Sprite 5 position and control data
$DFF16C	SPR5DATA	W	●	●	●	Sprite 5 image data register A
$DFF16E	SPR5DATB	W	●	●	●	Sprite 5 image data register B
$DFF170	SPR6POS	W	●	●	●	Sprite 6 vert,horiz start pos data
$DFF172	SPR6CTL	W	●	●	●	Sprite 6 position and control data
$DFF174	SPR6DATA	W	●	●	●	Sprite 6 image data register A
$DFF176	SPR6DATB	W	●	●	●	Sprite 6 image data register B
$DFF178	SPR7POS	W	●	●	●	Sprite 7 vert,horiz start pos data
$DFF17A	SPR7CTL	W	●	●	●	Sprite 7 position and control data
$DFF17C	SPR7DATA	W	●	●	●	Sprite 7 image data register A
$DFF17E	SPR7DATB	W	●	●	●	Sprite 7 image data register B
$DFF180	COLOR00	W	●	●	●	Color table 0
$DFF182	COLOR01	W	●	●	●	Color table 1
$DFF184	COLOR02	W	●	●	●	Color table 2
$DFF186	COLOR03	W	●	●	●	Color table 3
$DFF188	COLOR04	W	●	●	●	Color table 4
$DFF18A	COLOR05	W	●	●	●	Color table 5
$DFF18C	COLOR06	W	●	●	●	Color table 6
$DFF18E	COLOR07	W	●	●	●	Color table 7
$DFF190	COLOR08	W	●	●	●	Color table 8
$DFF192	COLOR09	W	●	●	●	Color table 9
$DFF194	COLOR10	W	●	●	●	Color table 10
$DFF196	COLOR11	W	●	●	●	Color table 11
$DFF198	COLOR12	W	●	●	●	Color table 12
$DFF19A	COLOR13	W	●	●	●	Color table 13
$DFF19C	COLOR14	W	●	●	●	Color table 14
$DFF19E	COLOR15	W	●	●	●	Color table 15
$DFF1A0	COLOR16	W	●	●	●	Color table 16
$DFF1A2	COLOR17	W	●	●	●	Color table 17
$DFF1A4	COLOR18	W	●	●	●	Color table 18
$DFF1A6	COLOR19	W	●	●	●	Color table 19
$DFF1A8	COLOR20	W	●	●	●	Color table 20
$DFF1AA	COLOR21	W	●	●	●	Color table 21
$DFF1AC	COLOR22	W	●	●	●	Color table 22
$DFF1AE	COLOR23	W	●	●	●	Color table 23
$DFF1B0	COLOR24	W	●	●	●	Color table 24
$DFF1B2	COLOR25	W	●	●	●	Color table 25
$DFF1B4	COLOR26	W	●	●	●	Color table 26
$DFF1B6	COLOR27	W	●	●	●	Color table 27
$DFF1B8	COLOR28	W	●	●	●	Color table 28
$DFF1BA	COLOR29	W	●	●	●	Color table 29
$DFF1BC	COLOR30	W	●	●	●	Color table 30
$DFF1BE	COLOR31	W	●	●	●	Color table 31
$DFF1C0	HTOTAL	W		●	●	Highest number count, horiz line (VARBEAMEN=1)
$DFF1C2	HSSTOP	W		●	●	Horizontal line position for HSYNC stop
$DFF1C4	HBSTRT	W		●	●	Horizontal line position for HBLANK start
$DFF1C6	HBSTOP	W		●	●	Horizontal line position for HBLANK stop
$DFF1C8	VTOTAL	W		●	●	Highest numbered vertical line (VARBEAMEN=1)
$DFF1CA	VSSTOP	W		●	●	Vertical line position for VSYNC stop
$DFF1CC	VBSTRT	W		●	●	Vertical line for VBLANK start
$DFF1CE	VBSTOP	W		●	●	Vertical line for VBLANK stop
$DFF1D0	SPRHSTRT	W		●	●	UHRES sprite vertical start
$DFF1D2	SPRHSTOP	W		●	●	UHRES sprite vertical stop
$DFF1D4	BPLHSTRT	W		●	●	UHRES bit plane vertical start
$DFF1D6	BPLHSTOP	W		●	●	UHRES bit plane vertical stop
$DFF1D8	HHPOSW	W		●	●	DUAL mode hires H beam counter write
$DFF1DA	HHPOSR	R		●	●	DUAL mode hires H beam counter read
$DFF1DC	BEAMCON0	W		●	●	Beam counter control register (SHRES,UHRES,PAL)
$DFF1DE	HSSTRT	W		●	●	Horizontal sync start (VARHSY)
$DFF1E0	VSSTRT	W		●	●	Vertical sync start (VARVSY)
$DFF1E2	HCENTER	W		●	●	Horizontal position for Vsync on interlace
$DFF1E4	DIWHIGH	W		●	●	Display window - upper bits for start/stop
$DFF1E6	BPLHMOD	W			●	UHRES bit plane modulo
$DFF1E8	SPRHPTH	W			●	UHRES sprite pointer (high 5 bits)
$DFF1EA	SPRHPTL	W			●	UHRES sprite pointer (low 15 bits)
$DFF1EC	BPLHPTH	W			●	VRam (UHRES) bitplane pointer (hi 5 bits)
$DFF1EE	BPLHPTL	W			●	VRam (UHRES) bitplane pointer (lo 15 bits)
$DFF1FC	FMODE	W			●	Fetch mode register

ADKCONR¶

Registers: ADKCONR $DFF010 (R), ADKCON $DFF09E (W)
Description: Audio, Disk, UART control (read/write pair)

ADKCONR reads the Audio/Disk/UART control state; ADKCON is the write-side register. Bit 15 selects set/clear semantics: bits written as zero are left unchanged.

Bit	Function	Description
15	SET/CLEAR	Set/clear control bit
14-13	PRECOMP	Precompensation: 00 none, 01 140 ns, 10 280 ns, 11 560 ns
12	MFMPREC	1 = MFM precomp, 0 = GCR precomp
11	UARTBRK	Force UART break (clear TXD)
10	WORDSYNC	Synchronize disk read on the word in DSKSYNC
09	MSBSYNC	Synchronize disk read on the MSB (GCR)
08	FAST	Disk clock rate: 1 = fast (2 us), 0 = slow (4 us)
07	USE3PN	Audio channel 3 modulates no following channel period
06	USE2P3	Channel 2 modulates channel 3 period
05	USE1P2	Channel 1 modulates channel 2 period
04	USE0P1	Channel 0 modulates channel 1 period
03	USE3VN	Audio channel 3 modulates no following channel volume
02	USE2V3	Channel 2 modulates channel 3 volume
01	USE1V2	Channel 1 modulates channel 2 volume
00	USE0V1	Channel 0 modulates channel 1 volume

If both period and volume modulation are enabled for the same channel, successive AUDxDAT words alternate between volume and period data.

AUDxDAT¶

Registers: AUD0DAT $DFF0AA (W), AUD1DAT $DFF0BA (W), AUD2DAT $DFF0CA (W), AUD3DAT $DFF0DA (W)
Description: Audio channel x DMA data buffer

This register family is the audio channel x (x = 0..3) DMA data buffer. Each word contains two signed 8-bit samples, output sequentially through the D/A converter. Audio DMA normally loads the register from Chip RAM, but the processor can also write it directly. When the programmed DMA length has been exhausted and the buffered data has been consumed, the corresponding audio-channel interrupt request is set.

AUDxLCH / AUDxLCL¶

Registers: AUD0LCH $DFF0A0 (W), AUD0LCL $DFF0A2 (W), AUD1LCH $DFF0B0 (W), AUD1LCL $DFF0B2 (W), AUD2LCH $DFF0C0 (W), AUD2LCL $DFF0C2 (W), AUD3LCH $DFF0D0 (W), AUD3LCL $DFF0D2 (W)
Description: Audio channel x DMA location (high/low pointer words)

Each AUDxLCH/AUDxLCL pair contains the starting address of audio channel x DMA data. The high register supplies the upper address bits and the low register the low 15 bits. Unlike a running DMA pointer, this location value only needs to be reloaded when the sample data is moved to a different memory address.

AUDxLEN¶

Registers: AUD0LEN $DFF0A4 (W), AUD1LEN $DFF0B4 (W), AUD2LEN $DFF0C4 (W), AUD3LEN $DFF0D4 (W)
Description: Audio channel x DMA length

AUDxLEN contains the length, in words, of the DMA data for audio channel x.

AUDxPER¶

Registers: AUD0PER $DFF0A6 (W), AUD1PER $DFF0B6 (W), AUD2PER $DFF0C6 (W), AUD3PER $DFF0D6 (W)
Description: Audio channel x period

AUDxPER contains the period (rate) for audio channel x DMA data transfer. The documented minimum period is 124 clocks; smaller programmed values should not be used.

AUDxVOL¶

Registers: AUD0VOL $DFF0A8 (W), AUD1VOL $DFF0B8 (W), AUD2VOL $DFF0C8 (W), AUD3VOL $DFF0D8 (W)
Description: Audio channel x volume

AUDxVOL sets the volume for audio channel x. Bits 5-0 select one of 64 linear levels; bit 6 forces maximum volume. Bits 15-7 are unused.

Bits	Function
15-07	Not used
06	Force maximum volume
05-00	Linear volume level (000000 = off, 111111 = level 63)

BEAMCON0¶

Registers: BEAMCON0 $DFF1DC (W)
Description: Beam counter control register (SHRES,UHRES,PAL)

BEAMCON0 controls programmable beam timing, synchronization polarity and use of the alternate high-resolution beam counter.

Bit	Function
15	Unused
14	HARDDIS
13	LPENDIS
12	VARVBEN
11	LOLDIS
10	CSCBEN
09	VARVSYEN
08	VARHSYEN
07	VARBEAMEN
06	DUAL
05	PAL
04	VARCSYEN
03	Unused (formerly BLANKEN)
02	CSYTRUE
01	VSYTRUE
00	HSYTRUE

HARDDIS disables the hardwired display-window limits. LPENDIS selects whether beam-position reads use the light-pen latch. VARVBEN, VARVSYEN, VARHSYEN, VARBEAMEN and VARCSYEN enable the programmable blank/sync/beam comparators. DUAL selects the alternate horizontal beam counter, PAL selects PAL timing in normal mode, and the three *TRUE bits select sync polarities.

BLTAFWM¶

Registers: BLTAFWM $DFF044 (W), BLTALWM $DFF046 (W)
Description: Blitter first/last word masks for source A

The patterns in the two registers are "anded" with the first and last words of each line of data from Source A into the Blitter. A zero in any bit overrides data from Source A. These registers should be set to all "ones" for fill mode or for line drawing mode.

BLTCON0¶

Registers: BLTCON0 $DFF040 (W), BLTCON1 $DFF042 (W), BLTCON0L $DFF05A (W)
Description: Blitter control registers

These two control registers are used together to control blitter operations. There are 2 basic modes, are and line, which are selected by bit 0 of BLTCON1, as show below.

Bit	BLTCON0 (AREA MODE)	BLTCON1 (AREA MODE)	Bit	BLTCON0 (LINE MODE)	BLTCON1 (LINE MODE)
15	ASH3	BSH3	15	ASH3	BSH3
14	ASH2	BSH2	14	ASH2	BSH2
13	ASH1	BSH1	13	ASH1	BSH1
12	ASA0	BSH0	12	ASH0	BSH0
11	USEA	0	11	1	0
10	USEB	0	10	0	0
09	USEC	0	09	1	0
08	USED	0	08	1	0
07	LF7	DOFF	07	LF7	DPFF
06	LF6	0	06	LF6	SIGN
05	LF5	0	05	LF5	OVF
04	LF4	EFE	04	LF4	SUD
03	LF3	IFE	03	LF3	SUL
02	LF2	FCI	02	LF2	AUL
01	LF1	DESC	01	LF1	SING
00	LF0	LINE(=0)	00	LF0	LINE(=1)

Function	Description
ASH3-0	Shift value of A source
BSH3-0	Shift value of B source and line texture
USEA	Mode control bit to use source A
USEB	Mode control bit to use source B
USEC	Mode control bit to use source C
USED	Mode control bit to use destination D
LF7-0	Logic function minterm select lines
EFE	Exclusive fill enable
IFE	Inclusive fill enable
FCI	Fill carry input
DESC	Descending (dec address)control bit
LINE	Line mode control bit
SIGN	Line draw sign flag
OVF	Line/draw r/l word overflow flag
SUD	Line draw, Sometimes up or down (=AUD)
SUL	Line draw, Sometimes up or left
AUL	Line draw, Always up or left
SING	Line draw, Single bit per horiz line. Disables the D output- for external ALUs
DOFF	The cycle occurs normally, but the data bus is tristate (hires chips only)

BLTDDAT¶

Registers: BLTDDAT $DFF000 (ER)
Description: Blitter dest. early read (dummy address)

This register holds the data resulting from each word of Blitter operation until it is sent to a RAM destination. This is a dummy address and cannot be read by the microprocessor. The transfer is automatic during Blitter operation.

BLTSIZE¶

Registers: BLTSIZE $DFF058 (W)
Description: Blitter start and size (win/width,height)

This register contains the width and height of the blitter operation (in line mode width must = 2, height = line length). Writing to this register will start the Blitter, and should be done last, after all pointers and control registers have been initialized.

Bit	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
Value	H9	H8	H7	H6	H5	H4	H3	H2	H1	H0	W5	W4	W3	W2	W1	W0

H = Height = Vertical lines (10 bits = 1024 lines max) W = Width = Horiz pixels (6 bits = 64 words = 1024 pixels max)

BLTSIZH¶

Registers: BLTSIZH $DFF05E (W)
Description: Blitter H size and start (for 11 bit H size)

Bit	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
Value	0	0	0	0	0	W10	W9	W8	W7	W6	W5	W4	W3	W2	W1	W0

BLTSIZV¶

Registers: BLTSIZV $DFF05C (W)
Description: Blitter V size (for 15 bit vertical size)

Bit	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
Value	0	H14	H13	H12	H11	H10	H9	H8	H7	H6	H5	H4	H3	H2	H1	H0

These are the blitter size regs for blits larger than the earlier chips could accept. The original commands are retained for compatibility. BLTSIZV should be written first, followed by BLTSIZH, which starts the blitter. BLTSIZV need not be rewritten for subsequent bits if the vertical size is the same. Max size of blit 32k pixels * 32k lines.

BLTxDAT¶

Registers: BLTCDAT $DFF070 (W), BLTBDAT $DFF072 (W), BLTADAT $DFF074 (W)
Description: Blitter source x data registers

These registers hold source x data (x = A, B, C) for the Blitter. They are normally loaded by the Blitter DMA channels, but they may also be preloaded by the processor. In line mode, BLTADAT is used as an index register and BLTBDAT provides the line texture.

BLTxMOD¶

Registers: BLTCMOD $DFF060 (W), BLTBMOD $DFF062 (W), BLTAMOD $DFF064 (W), BLTDMOD $DFF066 (W)
Description: Blitter modulo registers

Each Blitter source (A, B, C) and destination (D) has its own modulo. The signed modulo value is added to that channel's address at the end of each line so the pointer advances to the start of the next line. Separate modulos allow source and destination rasters to have different row strides.

BLTxPTH / BLTxPTL¶

Registers: BLTCPTH $DFF048 (W), BLTCPTL $DFF04A (W), BLTBPTH $DFF04C (W), BLTBPTL $DFF04E (W), BLTAPTH $DFF050 (W), BLTAPTL $DFF052 (W), BLTDPTH $DFF054 (W), BLTDPTL $DFF056 (W)
Description: Blitter source/destination pointer registers

Each BLTxPTH/BLTxPTL pair contains the DMA address for Blitter source x (A, B, C) or destination D. The pointer must be initialized to the start of the data before a blit. When the Blitter finishes, it contains the final data address after the normal increments and modulo adjustments.

BPLCON0¶

Registers: BPLCON0 $DFF100 (W)
Description: Bitplane control (miscellaneous control bits)

BPLCON0 selects the main display modes and several video-control functions.

Bit	Function	Description
15	HIRES	High-resolution display mode
14-12	BPUx	Number of bitplanes in use
11	HAM	Hold-And-Modify mode
10	DPF	Dual-playfield mode; with 6 planes, HAM=0 and DPF=0, selects Extra-Halfbrite behavior
09	COLOR	Enable color-burst output
08	GAUD	Genlock audio enable on the ZD pin during blanking
07	UHRES	Enable Ultra-Hi-Res pointers; also disables hard display-window stops
06	SHRES	Super-hi-res mode (35 ns pixel width)
05	BYPASS	Bypass the color table and output 8-bit bitplane data directly
04	BPU3	Additional bitplane-count bit
03	LPEN	Light-pen enable
02	LACE	Interlace enable
01	ERSY	External resync; HSYNC/VSYNC pads become inputs
00	ECSENA	Enable ECS-dependent BPLCON3 functions

When ECSENA is low, BRDRBLNK, BRDNTRAN, ZDCLKEN, BRDSPRT and EXTBLKEN in BPLCON3 are inhibited even if programmed.

BPLCON1¶

Registers: BPLCON1 $DFF102 (W)
Description: Bitplane control (scroll value)

BPLCON1 contains the horizontal scroll values for playfield 1 and playfield 2. On the enhanced chip sets the scroll range is extended for 32- and 64-bit fetch modes, with the least-significant scroll increment corresponding to a 35 ns SHRES pixel.

Bit	Function
15	PF2H7
14	PF2H6
13	PF2H1
12	PF2H0
11	PF1H7
10	PF1H6
09	PF1H1
08	PF1H0
07-04	PF2H5-PF2H2
03-00	PF1H5-PF1H2

BPLCON2¶

Registers: BPLCON2 $DFF104 (W)
Description: Bitplane control (video priority control)

BPLCON2 controls playfield/sprite priority and several AGA/ECS video and genlock functions.

Bit	Function	Description
15	x	Don't care; write 0 for upward compatibility
14-12	ZDBPSELx	Select bitplane mirrored to ZD when ZDBPEN is enabled
11	ZDBPEN	Mirror the selected bitplane on ZD
10	ZDCTEN	Mirror bit 15 of the active high color-table entry on ZD
09	KILLEHB	Disable Extra-Halfbrite mode
08	RDRAM	Select color-table read instead of write
07	SOGEN	Force SOG output high
06	PF2PRI	Give playfield 2 priority over playfield 1
05-03	PF2P2-PF2P0	Playfield 2 priority relative to sprites
02-00	PF1P2-PF1P0	Playfield 1 priority relative to sprites

BPLCON3¶

Registers: BPLCON3 $DFF106 (W)
Description: Bitplane control (enhanced features)

BPLCON3 contains enhanced palette, sprite-resolution, border and genlock controls.

Bit	Function	Description
15-13	BANKx	Select one of eight color-register banks
12-10	PF2OFx	Color-table offset for playfield 2 in dual-playfield mode
09	LOCT	Select low-order RGB palette bits for subsequent color writes
08	x	Don't care; write 0 for upward compatibility
07-06	SPRESx	Sprite resolution: ECS default, LORES, HIRES or SHRES
05	BRDRBLNK	Blank the border instead of displaying color 0
04	BRDNTRAN	Make border non-transparent for genlock
03	x	Don't care; write 0 for upward compatibility
02	ZDCLKEN	Output a 14 MHz clock on ZD; overrides other ZD functions
01	BRDSPRT	Enable sprites outside the display window
00	EXTBLKEN	Make BLANK output programmable

PF2OFx encodes offsets 0, 2, 4, 8, 16, 32, 64, 128. The border and external-blank functions are inhibited while BPLCON0.ECSENA is low.

BPLCON4¶

Registers: BPLCON4 $DFF10C (W)
Description: Bitplane control (bitplane and sprite-masks)

BPLCON4 is an AGA register used to modify bitplane palette addressing and to select sprite palette bases.

Bits	Function	Description
15-08	BPLAMx	8-bit value XORed with the bitplane color address before palette lookup
07-04	ESPRMx	Four high-order color-table address bits for even sprites (SPR0,2,4,6); default 0001
03-00	OSPRMx	Four high-order color-table address bits for odd sprites (SPR1,3,5,7); default 0001

BPLHDAT¶

Registers: BPLHDAT $DFF07A (W)
Description: External UHRES bitplane cycle identifier

This register identifies the external UHRES bitplane cycle on the RGA bus. When the UHRES bitplane pointer address is valid, BPLHDAT is emitted as the cycle identifier so external logic can recognize the special VRAM access.

BPLHMOD¶

Registers: BPLHMOD $DFF1E6 (W)
Description: UHRES bit plane modulo

This is the number (sign extended) that is added to the UHRES bitplane pointer (BPLHPTx) every line, and then another 2 is added, just like the other modulos.

BPLHPTH¶

Registers: BPLHPTH $DFF1EC (W), BPLHPTL $DFF1EE (W)
Description: UHRES (VRAM) bitplane pointer

When UHRES is enabled, this pointer comes out on the 2nd 'free' cycle after the start of each horizontal line. It‘s modulo is added every time it comes out. ’free' means priority above the copper and below the fixed stuff (audio,sprites….). BPLHDAT comes out as an identifier on the RGA lines when the pointer address is valid so that external detectors can use this to do the special cycle for the VRAMs, The SPRHDAT gets the first and third free cycles.

BPLHSTOP¶

Registers: BPLHSTOP $DFF1D6 (W)
Description: UHRES bit plane vertical stop

Bit	Name
15	BPLHWRM
14-11	Unused
10-0	V10-V0

BPLHWRM = Swaps the polarity of ARW* when the BPLHDAT comes out so that external devices can detect the RGA and put things into memory (ECS and later versions).

BPLHSTRT¶

Registers: BPLHSTRT $DFF1D4 (W)
Description: UHRES bit plane vertical start

This controls the line when the data fetch starts for the BPLHPTx pointers. V10-V0 on DB10-0.

BPLxDAT¶

Registers: BPL1DAT $DFF110 (W), BPL2DAT $DFF112 (W), BPL3DAT $DFF114 (W), BPL4DAT $DFF116 (W), BPL5DAT $DFF118 (W), BPL6DAT $DFF11A (W), BPL7DAT $DFF11C (W), BPL8DAT $DFF11E (W)
Description: Bitplane data registers

These registers receive bitplane DMA data fetched from RAM. They may also be written by the processor. Together they form the parallel-to-serial buffers for up to eight bitplanes; writing bitplane 1 triggers the parallel-to-serial conversion for the current word group. The most-significant bit is displayed first, so it appears at the left.

BPL1MOD / BPL2MOD¶

Registers: BPL1MOD $DFF108 (W), BPL2MOD $DFF10A (W)
Description: Bitplane modulo registers

BPL1MOD and BPL2MOD contain the modulos for odd and even bitplanes. At the end of each display line the appropriate signed modulo is added to the bitplane pointer so it addresses the first word of the next line. Separate odd/even modulos allow the two groups of planes to have different row strides.

BPLxPTH / BPLxPTL¶

Registers: BPL1PTH $DFF0E0 (W), BPL1PTL $DFF0E2 (W), BPL2PTH $DFF0E4 (W), BPL2PTL $DFF0E6 (W), BPL3PTH $DFF0E8 (W), BPL3PTL $DFF0EA (W), BPL4PTH $DFF0EC (W), BPL4PTL $DFF0EE (W), BPL5PTH $DFF0F0 (W), BPL5PTL $DFF0F2 (W), BPL6PTH $DFF0F4 (W), BPL6PTL $DFF0F6 (W), BPL7PTH $DFF0F8 (W), BPL7PTL $DFF0FA (W), BPL8PTH $DFF0FC (W), BPL8PTL $DFF0FE (W)
Description: Bitplane pointer registers

Each BPLxPTH/BPLxPTL pair contains the DMA pointer for bitplane x. The pointers are dynamic: during display DMA they advance as words are fetched, and at the end of the fetch line the corresponding bitplane modulo is added to position the pointer for the next line.

CLXCON¶

Registers: CLXCON $DFF098 (W)
Description: Collision control

This register controls which bitplanes are included (enabled) in collision detection, and their required state if included. It also controls the individual inclusion of odd numbered sprites in the collision detection, by logically ORing them with their correspond- ing even numbered sprite. Writing to this register resets the bits in CLXCON2.

Bit	Function	Description
15	ENSP7	Enable Sprite 7 (ORed with Sprite 6)
14	ENSP5	Enable Sprite 5 (ORed with Sprite 4)
13	ENSP3	Enable Sprite 3 (ORed with Sprite 2)
12	ENSP1	Enable Sprite 1 (ORed with Sprite 0)
11	ENSP6	Enable bit plane 6 (match reqd. for collision)
10	ENSP5	Enable bit plane 5 (match reqd. for collision)
09	ENSP4	Enable bit plane 4 (match reqd. for collision)
08	ENSP3	Enable bit plane 3 (match reqd. for collision)
07	ENSP2	Enable bit plane 2 (match reqd. for collision)
06	ENSP1	Enable bit plane 1 (match reqd. for collision)
05	ENSP6	Match value for bit plane 6 collision
04	ENSP5	Match value for bit plane 5 collision
03	ENSP4	Match value for bit plane 4 collision
02	ENSP3	Match value for bit plane 3 collision
01	ENSP2	Match value for bit plane 2 collision
00	ENSP1	Match value for bit plane 1 collision

CLXCON2¶

Registers: CLXCON2 $DFF10E (W)
Description: Extended collision control

This reg controls when bit planes 7 and 8 are included in collision detection, and there required state if included. Contents of this register are reset by a write to CLXCON.

BITS INITIALIZED BY RESET

Bit	Function	Description
15-08	Unused
07	ENBP8	Enable bit plane 8 (match reqd. for collision)
06	ENBP7	Enable bit plane 7 (match reqd. for collision)
05-02	Unused
01	MVBP8	Match value for bit plane 8 collision
00	MVBP7	Match value for bit plane 7 collision

Note: Disable bit planes cannot prevent collisions. Therefore if all bitplanes are disabled, collision will be continuous, regardless of the match values.

CLXDAT¶

Registers: CLXDAT $DFF00E (R)
Description: Collision data reg. (read and clear)

This address reads (and clears) the collision detection reg. The bit assignments are :

Note:
Playfield 1 is all odd numbered enabled bit planes.
Playfield 2 is all even numbered enabled bit planes.

Bit	Collision registered
15	Not used
14	Sprite 4 (or 5) to Sprite 6 (or 7)
13	Sprite 2 (or 3) to Sprite 6 (or 7)
12	Sprite 2 (or 3) to Sprite 4 (or 5)
11	Sprite 0 (or 1) to Sprite 6 (or 7)
10	Sprite 0 (or 1) to Sprite 4 (or 5)
09	Sprite 0 (or 1) to Sprite 2 (or 3)
08	Playfield 2 to Sprite 6 (or 7)
07	Playfield 2 to Sprite 4 (or 5)
06	Playfield 2 to Sprite 2 (or 3)
05	Playfield 2 to Sprite 0 (or 1)
04	Playfield 1 to Sprite 6 (or 7)
03	Playfield 1 to Sprite 4 (or 5)
02	Playfield 1 to Sprite 2 (or 3)
01	Playfield 1 to Sprite 0 (or 1)
00	Playfield 1 to Playfield 2

COLORxx¶

Registers: COLOR00 $DFF180 (W), COLOR01 $DFF182 (W), COLOR02 $DFF184 (W), COLOR03 $DFF186 (W), COLOR04 $DFF188 (W), COLOR05 $DFF18A (W), COLOR06 $DFF18C (W), COLOR07 $DFF18E (W), COLOR08 $DFF190 (W), COLOR09 $DFF192 (W), COLOR10 $DFF194 (W), COLOR11 $DFF196 (W), COLOR12 $DFF198 (W), COLOR13 $DFF19A (W), COLOR14 $DFF19C (W), COLOR15 $DFF19E (W), COLOR16 $DFF1A0 (W), COLOR17 $DFF1A2 (W), COLOR18 $DFF1A4 (W), COLOR19 $DFF1A6 (W), COLOR20 $DFF1A8 (W), COLOR21 $DFF1AA (W), COLOR22 $DFF1AC (W), COLOR23 $DFF1AE (W), COLOR24 $DFF1B0 (W), COLOR25 $DFF1B2 (W), COLOR26 $DFF1B4 (W), COLOR27 $DFF1B6 (W), COLOR28 $DFF1B8 (W), COLOR29 $DFF1BA (W), COLOR30 $DFF1BC (W), COLOR31 $DFF1BE (W)
Description: Color table registers 0 through 31

There are 32 color registers (COLOR00-COLOR31). With AGA color banking they address the 256-entry palette. BPLCON3.LOCT selects whether writes update the high or low four bits of each RGB component; writing the high-order set also preserves backward-compatible 12-bit color behavior.

LOCT	Bits 15-12	Bits 11-8	Bits 7-4	Bits 3-0
0	T000	R7-R4	G7-G4	B7-B4
1	0000	R3-R0	G3-G0	B3-B0

T is the transparency/genlock bit; R, G, and B are the red, green, and blue component bits.

COP1LCH¶

Registers: COP1LCH $DFF080 (W), COP1LCL $DFF082 (W)
Description: Copper first location pointer

These registers contain a jump address. See COPINS for a complete description.

COP2LCH¶

Registers: COP2LCH $DFF084 (W), COP2LCL $DFF086 (W)
Description: Copper second location pointer

These registers contain a jump address. See COPINS for a complete description.

COPCON¶

Registers: COPCON $DFF02E (W)
Description: Coprocessor control

This is a-1 bit register that when set true, allows the coprocessor to access the blitter hardware. This bit is cleared power on reset, so that the coprocessor cannot access the blitter hardware.

BIT# NAME FUNCTION Coprocessor danger mode. Allows coprocessor access to all RGA registers if true. 01 CDANG (if 0, access to RGA>DFF07E) (On old chips access to only RGA>DFF03E if CDANG=1) (see VPOSR)

COPINS¶

Registers: COPINS $DFF08C (S)
Description: Coprocessor inst fetch identify

This is a dummy address that is generated by the coprocessor whenever it is loading instructions into its own instruction register. This actually occurs every coprocessor cycle except for the second (IR2) cycle of the MOVE instruction. The three types of instructions are shown below.

MOVE Move immediate to dest Wait until beam counter is equal to, or greater than. WAIT (Keeps coprocessor off of bus until beam position has been reached) Skip if beam counter is equal to, or greater than. SKIP (Skips following MOVE inst. unless beam position has been reached)

Bit	MOVE IR1	MOVE IR2	WAIT UNTIL IR1	WAIT UNTIL IR2	SKIP IF IR1	SKIP IF IR2
15	0	RD15	VP7	BFD	VP7	BFD
14	0	RD14	VP6	VE6	VP6	VE6
13	0	RD13	VP5	VE5	VP5	VE5
12	0	RD12	VP4	VE4	VP4	VE4
11	0	RD11	VP3	VE3	VP3	VE3
10	0	RD10	VP2	VE2	VP2	VE2
09	0	RD09	VP1	VE1	VP1	VE1
08	DA8	RD08	VP0	VE0	VP0	VE0
07	DA7	RD07	HP8	HE8	HP8	HE8
06	DA6	RD06	HP7	HE7	HP7	HE7
05	DA5	RD05	HP6	HE6	HP6	HE6
04	DA4	RD04	HP5	HE5	HP5	HE5
03	DA3	RD03	HP4	HE4	HP4	HE4
02	DA2	RD02	HP3	HE3	HP3	HE3
01	DA1	RD01	HP2	HE2	HP2	HE2
00	0	RD00	1	0	1	1

Symbol	Description
IR1	First instruction register
IR2	Second instruction register
DA	Destination address for MOVE instruction. Fetched during IR1 time, used during IR2 time on RGA bus
RD	RAM Data moved by MOVE instruction at IR2 time directly from RAM to the address given by the DA field
VP	Vertical beam position comparison bit
HP	Horizontal beam position comparison bit
VE	Enable comparison (mask bit)
HE	Enable comparison (mask bit)

Note:
BFD = Blitter finished disable. When this bit is true, the blitter
finished flag will have no effect on the coprocessor. When this
bit is zero the blitter finished flag must be true (in addition
to the rest of the bit comparisons) before the coprocessor can
exit from it`s wait state, or skip over an instruction. Note
that the V7 comparison cannot be masked.

The coprocessor is basically a 2 cycle machine that requests the bus only during odd memory cycles. (4 memory cycles per in)

It has priority over the blitter and microprocessor.

There are only three types of instructions, MOVE immediate, WAIT UNTIL, and SKIP IF. All instructions require 2 bus cycles (and two instruction words). Since only the odd bus cycles are requested, 4 memory cycle times are required per instruction. (memory cycles are 280 ns).

There are two indirect jump registers COP1LC and COP2LC. These are 20 bit pointer registers whose contents are used to modify program counter for initialization or jumps.

They are transfered to the program counter whenever strobe address COPJMP1 or COPJMP2 are written. In addition COP1LC is automatically used at the beginning of each vertical blank time.

It is important that one of the jump registers be initialized and it`s jump strobe address hit, after power up but before coprocessor DMA is initialized. This insures a determined startup address, and state.

COPJMP1 / COPJMP2¶

Registers: COPJMP1 $DFF088 (S), COPJMP2 $DFF08A (S)
Description: Copper jump strobe registers

COPJMP1 and COPJMP2 are strobe addresses. Writing either one reloads the Copper program counter indirectly from COP1LC or COP2LC, respectively. The Copper itself may write these strobe addresses, allowing a Copper list to perform an indirect jump.

DDFSTRT¶

Registers: DDFSTRT $DFF092 (W), DDFSTOP $DFF094 (W)
Description: Display data-fetch start/stop

These registers control the horizontal timing of the beginning and end of the bit plane DMA timing display data fetch. The vertical bit plane DMA timing is identical to the display windows described above. The bit plane Modulos are dependent on the bit plane horizontal size, and on this data fetch window size.

Register bit assignment :

Bit	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
Value	0	0	0	0	0	0	0	0	H8	H7	H6	H5	H4	H3	H2	0

The tables below show the start and stop timing for different register contents

DDFSTRT (Left edge of display data fetch) :

PURPOSE	H8	H7	H6	H5	H4
Extra wide (max)	0	0	1	0	1
wide	0	0	1	1	0
normal	0	0	1	1	1
narrow	0	1	0	0	0

DDFSTOP (Right edge of display data fetch) :

PURPOSE	H8	H7	H6	H5	H4
narrow	1	1	0	0	1
normal	1	1	0	1	0
wide (max)	1	1	0	1	1

Note that these numbers will vary with variable beam counter mode set: (The maxes and mins, that is).

DENISEID¶

Registers: DENISEID $DFF07C (R)
Description: Chip revision level for Denise/Lisa (video out chip)

The original Denise (8362) does not have this register, so whatever value is left over on the bus from the last cycle will be there. ECS Denise (8373) returns hex (fc) in the lower 8 bits.Lisa returns hex (f8). The upper 8 bits of this Register are loaded from the serial mouse bus, and are reserved for future hardware implentation.

The 8 low-order bits are encoded as follows :

Bit	Description
7-4	Lisa/Denise/ECS Denise Revision level (decrement to bump revision level, hex F represents 0th rev. level).
3	Maintain as a 1 for future generation
2	When low indicates AA feature set (LISA)
1	When low indicates ECS feature set (LISA or ECS DENISE)
0	Maintain as a 1 for future generation

A proposed way to detect chip's revision through hardware poking :

is_AGA: move.w 0xdff07c,d0 moveq #31-1,d2 and.w #0xff,d0 check_loop: move.w 0xdff07C,d1 and.w #0xff,d1 cmp.b d0,d1 bne.b not_AGA dbf d2,check_loop or.b #0xf0,d0 cmp.b #0xf8,d0 bne.b not_AGA moveq #1,d0 rts not_AGA: moveq #0,d0 rts

DIWHIGH¶

Registers: DIWHIGH $DFF1E4 (W)
Description: Display window - upper bits for start/stop

This is an added register for Hires chips, and allows larger start & stop ranges. If it is not written, (DIWSTRT, DIWSTOP) description holds. If this register is written, direct start & stop positions anywhere on the screen. It doesn't affect the UHRES pointers.

Bit	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
Value	0	0	H10	H1	H0	V10	V9	V8	0	0	H10	H1	H0	V10	V9	V8
Field	stop	stop	stop	stop	stop	stop	stop	stop	start	start	start	start	start	start	start	start

H1 and H0 values define 70ns and 35ns increments respectively, and new LISA bits.

Note:
In all 3 display window registers, horizontal bit positions have been
renamed to reflect HIRES pixel increments, e.g. what used to be
called H0 is now referred to as H2.

DIWSTRT¶

Registers: DIWSTRT $DFF08E (W), DIWSTOP $DFF090 (W)
Description: Display window start/stop

These registers control the display window size and position, by locating the upper left and lower right corners.

Bit	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
Value	V7	V6	V5	V4	V3	V2	V1	V0	H9	H8	H7	H6	H5	H4	H3	H2

DIWSTRT is vertically restricted to the upper 2/3 of the display (V8=0), and horizontally restricted to the left 3/4 of the display (H8=0).

See DIWHIGH for exceptions.

DMACONR¶

Registers: DMACONR $DFF002 (R), DMACON $DFF096 (W)
Description: DMA control and status

This register controls all of the DMA channels, and contains blitter DMA status bits.

Bit	Function	Description
15	SET/CLR	written with a 1 get set or cleared Bits written with a zero are unchanged
14	BBUSY	Blitter busy status bit (read only)
13	BZERO	Blitter logic zero status bit (read only)
12	X
11	X	Blitter DMA priority (over CPU micro) (also called "blitter nasty")
10	BLTPRI	(disables /BLS pin, preventing micro from stealing any bus cycles while blitter DMA is running)
09	DMAEN	Enable all DMA below (also UHRES DMA)
08	BPLEN	Bit plane DMA enable
07	COPEN	Coprocessor DMA enable
06	BLTEN	Blitter DMA enable
05	SPREN	Sprite DMA enable
04	DSKEN	Disk DMA enable
03	AUD3EN	Audio channel 3 DMA enable
02	AUD2EN	Audio channel 2 DMA enable
01	AUD1EN	Audio channel 1 DMA enable
00	AUD0EN	Audio channel 0 DMA enable

DSKBYTR¶

Registers: DSKBYTR $DFF01A (R)
Description: Disk data byte and status read

This register is the Disk-Microprocessor data buffer. Data from the disk (in read mode) is loaded into this register one byte at a time, and bit 15 (DSKBYT) is set true.

Bit	Function	Description
15	DSKBYT	Disk byte ready (reset on read)
14	DMAON	DMAEN (DSKLEN) & DMAEN (DMACON) & DSKEN (DMACON)
13	DISKWRITE	Mirror of bit 14 (WRITE) in DSKLEN
12	WORDEQUAL	This bit true only while DSKSYNC register equals the data from disk
11-08	0	Not used
07-00	DATA	Disk byte data

DSKDATR¶

Registers: DSKDATR $DFF008 (ER), DSKDAT $DFF026 (W)
Description: Disk DMA data register

This register is the disk-DMA data buffer.It contains 2 bytes of data that are either sent to (write) or received from (read) the disk. The DMA controller automatically transfers data to or from this register and RAM, and when the DMA data is finished (length=0) it causes a disk block interrupt.

DSKLEN¶

Registers: DSKLEN $DFF024 (W)
Description: Disk length

Bit	Function	Description
15	DMAEN	Disk DMA enable
14	WRITE	Disk write (RAM or disk) if 1
13-0	LENGTH	Length (# of words) of DMA data.

DSKPTH¶

Registers: DSKPTH $DFF020 (W), DSKPTL $DFF022 (W)
Description: Disk DMA pointer

This pair of registers contains the 20 bit address of disk DMA data. These address registers must be initialized by the processor or coprocessor before disk DMA is enabled.

DSKSYNC¶

Registers: DSKSYNC $DFF07E (W)
Description: Disk sync pattern reg for disk read

FMODE¶

Registers: FMODE $DFF1FC (W)
Description: Fetch mode register

FMODE controls the AGA Chip RAM fetch mechanism for bitplanes and sprites.

Bit	Function	Description
15	SSCAN2	Global sprite scan-doubling enable
14	BSCAN2	Use the second playfield modulo on alternate lines for bitplane scan-doubling
13-04	—	Unused
03	SPAGEM	Sprite page mode (double CAS)
02	SPR32	32-bit sprite fetch mode
01	BPAGEM	Bitplane page mode (double CAS)
00	BPL32	32-bit bitplane fetch mode

PAGEM	32-bit	Fetch increment	Memory cycle	Bus width
0	0	2 bytes	normal CAS	16
0	1	4 bytes	normal CAS	32
1	0	4 bytes	double CAS	16
1	1	8 bytes	double CAS	32

The same four combinations apply independently to bitplanes (BPAGEM/BPL32) and sprites (SPAGEM/SPR32).

HBSTRT¶

Registers: HBSTRT $DFF1C4 (W), HBSTOP $DFF1C6 (W)
Description: Horizontal blanking start/stop

Bits 7-0 contain the stop and start positions, respectively, for programmed horizontal blanking in 280ns increments. Bits 10-8 provide a fine position control in 35ns increments.

Bit	Function	Description
15-11	0	Unused
10	H1	140ns
09	H1	70ns
08	H0	35ns
07	H10	35840ns
06	H9	17920ns
05	H8	8960ns
04	H7	4480ns
03	H6	2240ns
02	H5	1120ns
01	H4	560ns
00	H3	280ns

HCENTER¶

Registers: HCENTER $DFF1E2 (W)
Description: Horizontal position for Vsync on interlace

This is necessary for interlace mode with variable beam counters. See BEAMCON0 for when it affects chip outputs. See HTOTAL for bits.

HHPOSW¶

Registers: HHPOSW $DFF1D8 (W), HHPOSR $DFF1DA (R)
Description: DUAL-mode high-resolution horizontal beam counter

This the secondary beam counter for the faster mode, triggering the UHRES pointers & doing the comparisons for HBSTRT, HBSTOP, HTOTAL, HSSTRT, HSSTOP (See HTOTAL for bits)

HSSTOP¶

Registers: HSSTOP $DFF1C2 (W)
Description: Horizontal line position for HSYNC stop

Sets # of colour clocks for sync stop (HTOTAL for bits).

HSSTRT¶

Registers: HSSTRT $DFF1DE (W)
Description: Horizontal sync start (VARHSY)

Set # of colour clocks for sync start (HTOTAL for bits) See BEAMCON0 for details of when these 2 are active.

HTOTAL¶

Registers: HTOTAL $DFF1C0 (W)
Description: Highest number count, horiz line (VARBEAMEN=1)

Bit	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
Value	0	0	0	0	0	0	0	0	H8	H7	H6	H5	H4	H3	H2	H1

Horizontal line has these many + 1 280nS increments. If the pal bit & LOLDIS are not high, long line/short line toggle will occur, and there will be this many +2 every other line. Active if VARBEAMEN=1 or DUAL+1.

INTENAR¶

Registers: INTENAR $DFF01C (R), INTENA $DFF09A (W)
Description: Interrupt enable control

This register contains interrupt enable bits. The bit assignment for both the request, and enable registers is given below.

Bit	Function	Level	Description
15	SET/CLR		Set/clear control bit. Determines if bits written with a 1 get set or cleared. Bits written with a zero are always unchanged.
14	INTEN		Master interrupt (enable only, no request)
13	EXTER	6	External interrupt
12	DSKSYN	5	Disk sync register (DSKSYNC) matches disk
11	RBF	5	Serial port receive buffer full
10	AUD3	4	Audio channel 3 block finished
09	AUD2	4	Audio channel 2 block finished
08	AUD1	4	Audio channel 1 block finished
07	AUD0	4	Audio channel 0 block finished
06	BLIT	3	Blitter has finished
05	VERTB	3	Start of vertical blank
04	COPER	3	Coprocessor
03	PORTS	2	I/O Ports and timers
02	SOFT	1	Reserved for software initiated interrupt.
01	DSKBLK	1	Disk block finished
00	TBE	1	Serial port transmit buffer empty

INTREQR¶

Registers: INTREQR $DFF01E (R), INTREQ $DFF09C (W)
Description: Interrupt request control

This register contains interrupt request bits (or flags). These bits may be polled by the processor, and if enabled by the bits listed in the next register, they may cause processor interrupts. Both a set and clear operation are required to load arbitrary data into this register.

Bit	Function	Level	Description
15	SET/CLR		Set/clear control bit. Determines if bits written with a 1 get set or cleared. Bits written with a zero are always unchanged.
14	INTEN		Master interrupt (enable only, no request)
13	EXTER	6	External interrupt
12	DSKSYN	5	Disk sync register (DSKSYNC) matches disk
11	RBF	5	Serial port receive buffer full
10	AUD3	4	Audio channel 3 block finished
09	AUD2	4	Audio channel 2 block finished
08	AUD1	4	Audio channel 1 block finished
07	AUD0	4	Audio channel 0 block finished
06	BLIT	3	Blitter has finished
05	VERTB	3	Start of vertical blank
04	COPER	3	Coprocessor
03	PORTS	2	I/O Ports and timers
02	SOFT	1	Reserved for software initiated interrupt.
01	DSKBLK	1	Disk block finished
00	TBE	1	Serial port transmit buffer empty

JOY0DAT¶

Registers: JOY0DAT $DFF00A (R), JOY1DAT $DFF00C (R)
Description: Joystick/mouse counter data

These addresses each read a 16 bit register. These in turn are loaded from the MDAT serial stream and are clocked in on the rising edge of SCLK. MLD output is used to parallel load the external parallel-to- serial converter.This in turn is loaded with the 4 quadrature inputs from each of two game controller ports (8 total) plus 8 miscellaneous control bits which are new for LISA and can be read in upper 8 bits of LISAID.

Register bits are as follows:

Mouse counter usage (pins 1,3 = Yclock, pins 2,4 = Xclock)

Register / Bit	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
JOY0DAT	Y7	Y6	Y5	Y4	Y3	Y2	Y1	Y0	X7	X6	X5	X4	X3	X2	X1	X0
JOY1DAT	Y7	Y6	Y5	Y4	Y3	Y2	Y1	Y0	X7	X6	X5	X4	X3	X2	X1	X0

0 = LEFT CONTROLLER PAIR, 1 = RIGHT CONTROLLER PAIR. (4 counters total).The bit usage for both left and right addresses is shown below. Each 6 bit counter (Y7-Y2,X7-X2) is clocked by 2 of the signals input from the mouse serial stream.

Starting with first bit received:

Serial Bit	Name	Description
0	M0H	JOY0DAT Horizontal Clock
1	M0HQ	JOY0DAT Horizontal Clock (quadrature)
2	M0V	JOY0DAT Vertical Clock
3	M0VQ	JOY0DAT Vertical Clock (quadrature)
4	M1V	JOY1DAT Horizontall Clock
5	M1VQ	JOY1DAT Horizontall Clock (quadrature)
6	M1V	JOY1DAT Vertical Clock
7	M1VQ	JOY1DAT Vertical Clock (quadrature)

Bits 1 and 0 of each counter (Y1-Y0,X1-X0) may be read to determine the state of the related input signal pair. This allows these pins to double as joystick switch inputs. Joystick switch closures can be deciphered as follows:

Direction	Pin	Counter bits
Forward	1	Y1 xor Y0 (BIT#09 xor BIT#08)
Left	3	Y1
Back	2	X1 xor X0 (BIT#01 xor BIT#00)
Right	4	X1

JOYTEST¶

Registers: JOYTEST $DFF036 (W)
Description: Write to all 4 joystick-mouse counters at once

Mouse counter write test data:

Register / Bit	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
JOY0DAT	Y7	Y6	Y5	Y4	Y3	Y2	Y1	Y0	X7	X6	X5	X4	X3	X2	X1	X0
JOY1DAT	Y7	Y6	Y5	Y4	Y3	Y2	Y1	Y0	X7	X6	X5	X4	X3	X2	X1	X0

POT0DAT¶

Registers: POT0DAT $DFF012 (R), POT1DAT $DFF014 (R)
Description: Potentiometer counter data

These addresses each read a pair of 8 bit pot counters. (4 counters total). The bit assignment for both addresses is shown below. The counters are stopped by signals from 2 controller connectors (left-right) with 2 pins each.

Register / Bit	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
RIGHT	Y7	Y6	Y5	Y4	Y3	Y2	Y1	Y0	X7	X6	X5	X4	X3	X2	X1	X0
LEFT	Y7	Y6	Y5	Y4	Y3	Y2	Y1	Y0	X7	X6	X5	X4	X3	X2	X1	X0

Loc.	Dir.	Sym.	Connector Pin	Paula Pin
RIGHT	Y	RX	9	33
RIGHT	X	RX	5	32
LEFT	Y	LY	9	36
LEFT	X	LX	5	35

With normal (NTSC or PAL) horiz. line rate, the pots will give a full scale (FF) reading with about 500kohms in one frame time. With proportionally faster horiz line times, the counters will count proportionally faster. This should be noted when doing variable beam displays.

POTGO¶

Registers: POTGO $DFF034 (W)
Description: Pot count start,pot pin drive enable data

POTINP¶

Registers: POTINP $DFF016 (R)
Description: Pot pin data read

This register controls a 4-bit bidirectional I/O port that shares the same four pins as the potentiometer counters.

Bit	Function	Description
15	OUTRY	Output enable for Paula pin 33
14	DATRY	I/O data, Paula pin 33
13	OUTRX	Output enable for Paula pin 32
12	DATRX	I/O data, Paula pin 32
11	OUTLY	Output enable for Paula pin 36
10	DATLY	I/O data, Paula pin 36
09	OUTLX	Output enable for Paula pin 35
08	DATLX	I/O data, Paula pin 35
07-01	—	Not used
00	START	Start pots (dump capacitors, start counters)

REFPTR¶

Registers: REFPTR $DFF028 (W)
Description: Refresh pointer

This register is used as a dynamic RAM refresh address generator. It's writable for test purposes only, and should never be written by the microprocessor.

SERDAT¶

Registers: SERDAT $DFF030 (W)
Description: Serial port data and stop bits write

This address writes data to a transmit data buffer. Data from this buffer is moved into a serial shift register for output transmission whenever it is empty. This sets the interrupt request TBE (transmit buffer empty).

A stop bit must be provided as part of the data word. The length of the data word is set by the position of the stop bit.

Bit	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
Value	0	0	0	0	0	0	S	D8	D7	D6	D5	D4	D3	D2	D1	D0

SERDATR¶

Registers: SERDATR $DFF018 (R)
Description: Serial port data and status read

This address reads data from a recive data buffer. Data in this buffer is loaded from a receiving shift register whenever it is full. Several interrupt request bits are also read at this address, along with the data as shown below.

Bit	Function	Description
15	OVRUN	Serial port receiver overun
14	RBF	Serial port receive buffer full (mirror)
13	TBE	Serial port transmit buffer empty (mirror)
12	TSRE	Serial port transmit shift reg. empty
11	RXD	RXD pin receives UART serial data for direct bit test by the micro.
10	X	Not used.
09	STP	Stop bit
08	STP-DB8	Stop bit if LONG, data bit if not.
07	DB7	Data bit.
06	DB6	Data bit.
05	DB5	Data bit.
04	DB4	Data bit.
03	DB3	Data bit.
02	DB2	Data bit.
01	DB1	Data bit.
00	DB0	Data bit.

SERPER¶

Registers: SERPER $DFF032 (W)
Description: Serial port period and control

This register contains the control bit LONG referred to above, and a 15 bit number defining the serial port Baud rate. If this number is N,then the baud rate is 1 bit every (N+1)*.2794 microseconds.

Bit	Function	Description
15	LONG	Defines serial receive as 9 bit word.
14-00	RATE	Defines baud rate=1/((N+1)*.2794 microseconds)

SPRHDAT¶

Registers: SPRHDAT $DFF078 (W)
Description: Ext. logic UHRES sprite pointer and data identifier

This identifies the cycle when this pointer address is on the bus accessing the memory.

SPRHPTH¶

Registers: SPRHPTH $DFF1E8 (W), SPRHPTL $DFF1EA (W)
Description: UHRES sprite pointer

This pointer is activated in the 1st and 3rd 'free' cycles (see BPLHPTx) after horizontal line start. It increments for the next line.

SPRHSTOP¶

Registers: SPRHSTOP $DFF1D2 (W)
Description: UHRES sprite vertical stop

Bit	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
Value	SPRHWRM	0	0	0	0	0	V10	V9	V8	V7	V6	V5	V4	V3	V2	V1

SPRHWRM = Swaps the polarity of ARW* when the SPRHDAT comes out so that external devices can detect the RGA and put things into memory. (ECS and later chips only)

SPRHSTRT¶

Registers: SPRHSTRT $DFF1D0 (W)
Description: UHRES sprite vertical start

Bit	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
Value	0	0	0	0	0	V10	V9	V8	V7	V6	V5	V4	V3	V2	V1	V0

SPRxCTL¶

Registers: SPR0CTL $DFF142 (W), SPR1CTL $DFF14A (W), SPR2CTL $DFF152 (W), SPR3CTL $DFF15A (W), SPR4CTL $DFF162 (W), SPR5CTL $DFF16A (W), SPR6CTL $DFF172 (W), SPR7CTL $DFF17A (W)
Description: Sprite position/control registers

Bit	Function	Description
15-08	EV7-EV0	End (stop) vertical value. Low 8 bits
07	ATT	Sprite attach control bit (odd sprites only)
06	SV9	Start vertical value 10th bit
05	EV9	End (stop) vertical value 10th bit
04	SH1=0	Start horizontal value, 70nS increment
03	SH0=0	Start horizontal value 35nS increment
02	SV8	Start vertical value 9th bit
01	EV8	End (stop) vertical value 9th bit
00	SH2	Start horizontal value, 140nS increment

SPRxDATA / SPRxDATB¶

Registers: SPR0DATA $DFF144 (W), SPR0DATB $DFF146 (W), SPR1DATA $DFF14C (W), SPR1DATB $DFF14E (W), SPR2DATA $DFF154 (W), SPR2DATB $DFF156 (W), SPR3DATA $DFF15C (W), SPR3DATB $DFF15E (W), SPR4DATA $DFF164 (W), SPR4DATB $DFF166 (W), SPR5DATA $DFF16C (W), SPR5DATB $DFF16E (W), SPR6DATA $DFF174 (W), SPR6DATB $DFF176 (W), SPR7DATA $DFF17C (W), SPR7DATB $DFF17E (W)
Description: Sprite image data registers

SPRxDATA and SPRxDATB buffer the two bitplanes of sprite x image data. They are normally filled by sprite DMA, but may also be written by the processor. At the programmed horizontal position the buffers are loaded into shift registers and serialized to the display, most-significant bit first. Writing the A (DATA) buffer arms the sprite; writing SPRxCTL disables it.

SPRxPOS¶

Registers: SPR0POS $DFF140 (W), SPR1POS $DFF148 (W), SPR2POS $DFF150 (W), SPR3POS $DFF158 (W), SPR4POS $DFF160 (W), SPR5POS $DFF168 (W), SPR6POS $DFF170 (W), SPR7POS $DFF178 (W)
Description: Sprite start-position registers

Bit	Function	Description
15-08	SV7-SV0	Start vertical value.High bit (SV8) is in SPRxCTL registers.
07-00	SH10-SH3	Sprite horizontal start value. Low order 3 bits are in SPRxCTL registers. If SSCAN2 bit in FMODE is set, then disable SH10 horizontal coincidence detect.This bit is then free to be used by ALICE as an individual scan double enable.

SPRxPTH / SPRxPTL¶

Registers: SPR0PTH $DFF120 (W), SPR0PTL $DFF122 (W), SPR1PTH $DFF124 (W), SPR1PTL $DFF126 (W), SPR2PTH $DFF128 (W), SPR2PTL $DFF12A (W), SPR3PTH $DFF12C (W), SPR3PTL $DFF12E (W), SPR4PTH $DFF130 (W), SPR4PTL $DFF132 (W), SPR5PTH $DFF134 (W), SPR5PTL $DFF136 (W), SPR6PTH $DFF138 (W), SPR6PTL $DFF13A (W), SPR7PTH $DFF13C (W), SPR7PTL $DFF13E (W)
Description: Sprite DMA pointer registers

Each SPRxPTH/SPRxPTL pair contains the DMA address of sprite x data. The pointer registers must be initialized by the processor or Copper for each vertical field in which the sprite DMA data is to be used.

STREQU¶

Registers: STREQU $DFF038 (S), STRVBL $DFF03A (S), STRHOR $DFF03C (S), STRLONG $DFF03E (S)
Description: Refresh/synchronization strobe registers

One of the first 3 strobe addresses above, it is placed on the RGA bus during the first refresh time slot of every other line, to identify lines with long counts (228- NTSC, HTOTAL+2- VARBEAMEN=1 hires chips only).There are 4 refresh time slots and any not used for strobes will leave a null (1FE) address on the RGA bus.

VBSTRT¶

Registers: VBSTRT $DFF1CC (W), VBSTOP $DFF1CE (W)
Description: Vertical blanking start/stop

(V10-0 <- D10-0) Affects CSY pin if BLAKEN=1 and VSY pin if CSCBEN=1 (see BEAMCON0)

VHPOSR¶

Registers: VHPOSR $DFF006 (R), VHPOSW $DFF02C (W)
Description: Vertical/horizontal beam position read/write

Bit	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
Value	V7	V6	V5	V4	V3	V2	V1	V0	H8	H7	H6	H5	H4	H3	H2	H1

Resolution = 1/160 of screen width (280 ns).

VPOSR¶

Registers: VPOSR $DFF004 (R), VPOSW $DFF02A (W)
Description: Vertical position/frame state read/write

Bit	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
Value	LOF	I6	I5	I4	I3	I2	I1	I0	LOL	xx	xx	xx	xx	V10	V9	V8

LOF = Long frame(auto toggle control bit in BPLCON0)

I0-I6 Chip identification:

VSSTRT¶

Registers: VSSTRT $DFF1E0 (W), VSSTOP $DFF1CA (W)
Description: Vertical sync start/stop

VTOTAL¶

Registers: VTOTAL $DFF1C8 (W)
Description: Highest numbered vertical line (VARBEAMEN=1)

Its the line number to reset the counter, so theres this many + 1 in a field. The exception is if the LACE bit is set (BPLCON0), in which case every other field is this many + 2 and the short field is this many + 1.