Amiga Custom Chips — Hardware Reference

The Amiga's graphics and sound capabilities come from three custom chips — Agnus, Denise, and Paula — supported by two 8520 CIA (Complex Interface Adapter) chips. Together they provide hardware-accelerated graphics (Copper, Blitter, sprites, playfields), four-channel DMA audio, floppy disk I/O, and serial/parallel/keyboard interfaces. This article documents the hardware architecture from the Amiga Hardware Reference Manual (3rd Edition, Commodore-Amiga, 1992) — the register-level counterpart to the OS API articles — and the AGA (AA) third-generation chip set from the AA chip set feature summary (see AGA).

The three custom chips

Chip Role Key subsystems
Agnus (8361/8370/8371/8372A) DMA controller + coprocessors Copper, Blitter, bitplane DMA, sprite DMA, memory arbiter
Alice (AGA: 8374) Agnus successor Same as Agnus + 32-bit-wide display DMA
Denise (8362/8373) Display + collision detection Bitplane display, sprite display, color palette, mouse/joystick ports
Lisa (AGA: 8369) Denise successor Same as Denise + 8 bitplanes, 256×25-bit palette, HAM8
Paula (8364) Audio + I/O 4 audio channels, floppy disk controller, serial port, analog joystick

Chip memory vs fast memory

Custom chips can only access Chip RAM — memory accessible to both the CPU and the DMA channels. Fast RAM is CPU-only (no DMA access). The Blitter and Copper can only read/write Chip RAM. Attempting to use the Blitter on Fast memory may corrupt Chip memory contents.

Chip set Max Chip RAM Amiga model
Original OCS (8361 Agnus) 512 KB A1000
Fat Agnus (8370/8371) 512 KB + 512 KB "slow" Early A500/A2000
ECS Fat Agnus (8372A) 1 MB Most A500/A2000
ECS (A3000) 2 MB A3000
AGA (Alice) 2 MB A1200/A4000/CD32

The Copper

The Copper is a coprocessor within Agnus that can write to nearly all custom-chip registers synchronized to the video beam position. It is the primary tool for mid-screen register changes (color gradients, resolution switches, sprite repositioning).

Three instructions

Instruction Description
WAIT Wait for a specific video beam position (x, y), then continue
MOVE Write a 16-bit value to a hardware register
SKIP Skip the next instruction if the beam has passed a position (ECS only)

Each instruction is two 16-bit words in sequential Chip RAM. The Copper fetches via DMA during odd-numbered memory cycles only, avoiding collision with audio, disk, refresh, and sprite DMA (which use even cycles). During WAIT, the Copper uses zero bus bandwidth — it reads the beam counter directly.

Copper MOVE instruction:
  Word 1 (IR1): bit 0 = 0 (MOVE marker), bits 8-1 = register address
  Word 2 (IR2): bits 15-0 = data to write

Copper WAIT instruction:
  Word 1 (IR1): bit 0 = 1 (WAIT marker), bits 15-1 = vertical beam compare
  Word 2 (IR2): bits 15-1 = horizontal beam compare, bit 0 = beam enable bitmask

The Copper can write to any register at address $20 and above, or between $10-$20 if the COPCON "danger bit" is set. It cannot write below $10.

The Blitter

The Blitter (BLock Image Transferrer) is the second coprocessor in Agnus, used for: - Block memory copies — rectangular regions, approximately twice as fast as the 68000 (nearly 4 MB/s) - Line drawing — nearly 1 million pixels/second - Area fill — filling outlined shapes - Logical operations — any boolean function of up to three sources areas (A, B, C)

The Blitter is a word blitter (16-bit), not a bit blitter. It operates on three source areas (A, B, C) and produces a destination (D) using minterms — an 8-bit truth table selecting which of the 256 possible boolean combinations of A, B, C are set in the output. The minterm byte is written to the BLTAFWM/BLTBWM registers.

Common minterm Value Operation
C (cookie cut) $C0 Destination = C (source copy)
A OR C (merge) $FC Masked blit
A AND C (mask) $C8 Cookie cut with mask
A XOR C (invert) $C6 Toggle bits
~A AND C $30 Erase where A is set

The Blitter is asynchronous — once started (by writing BLTSIZE), the 680x0 continues executing. The Blitter steals memory cycles from the CPU, so CPU execution slows during active blits. The Blitter has descending mode (for overlapping regions), barrel shifting (1-15 bit pre-shift on A and B sources), and a "zero" flag for detecting all-zero results.

Sprites

Sprites are hardware graphic objects displayed independently of playfields, generated by 8 sprite DMA channels. Each basic sprite:

  • 16 pixels wide, any height (AGA fetches wider: 32 or 64 pixels — see AGA)
  • 3 colors + transparent (4 pixel values: 00, 01, 10, 11, transparent)
  • Positionable anywhere on screen via X,Y coordinates
  • Sprite pairs can be attached for 15 colors + transparent

Sprite DMA channels can be reused multiple times within the same display field — after producing the last line of a sprite on-screen, a channel is free for reuse lower on the screen. This means the Amiga can display far more than 8 simultaneous sprites (limited only by vertical spacing).

AGA additions: sprite resolution becomes selectable (LORES/HIRES/SHRES) independently of bitplane resolution, attached sprites work in all resolutions, sprites can be shown in the border (BRDRSPRT in BPLCON3), odd/even sprite color maps can be relocated (OSPRM/ESPRM mask fields), and sprites can be scan-doubled (see AGA).

Playfields (bitplanes)

Playfields are the background display layers, composed of bitplanes. Each bitplane is a single-bit-deep bitmap; multiple bitplanes are combined to produce color indices.

The table below shows for each bitplane depth (rows) the supported display resolutions per chip set (columns). LORES = 320×200/256, HIRES = 640×200/256, "+laced" doubles vertical resolution. SUPERHIRES (1280×200/256, AGA-only) and Productivity mode (640×480/576 at 31 kHz) are progressively introduced by ECS and AGA.

Bitplanes Colors OCS support ECS support AGA support
1 2 LORES, HIRES, LORES+laced, HIRES+laced OCS modes + Productivity (scan-doubled) OCS + ECS modes + SUPERHIRES, SUPERHIRES+laced
2 4 same as 1 bpl same same
3 8 same as 1 bpl same same
4 16 same as 1 bpl (1–2 bpl practical in HIRES+laced) same same
5 32 (EHB — extra half-bright) all OCS resolutions (interlaced marginal at 5–6 bpl) OCS modes + Productivity OCS + ECS modes + SUPERHIRES
6 64 (HAM — Hold and Modify) LORES, HIRES (interlaced limited) OCS modes + Productivity OCS + ECS modes + SUPERHIRES
7–8 128 / 256 (AGA only) ❌ not supported ❌ not supported LORES, HIRES, LORES+laced (full 8 bpl); HIRES+laced (6–8 bpl); SUPERHIRES (4–8 bpl); Productivity (8 bpl)

Key bandwidth constraints:

  • OCS (Agnus 8361/8370 + Denise 8362): 6 bitplane maximum in LORES/HIRES; interlaced modes are severely bandwidth-limited (16-bit DMA, no page mode). SUPERHIRES is absent.
  • ECS (Fat Agnus 8372A + Super Denise 8373): same 6-bpl cap as OCS, but introduces the Productivity mode at 31 kHz via scan-doubling. SUPERHIRES still absent.
  • AGA (Alice 8374 + Lisa 8369): the display DMA bus is 32 bits wide and supports FAST page mode, doubling bandwidth — 8 bpl achievable in nearly every mode. Introduces SUPERHIRES (14 MHz pixel clock), HAM8 (262144 colors displayed), and 4+4 dual playfield in all resolutions.

Display resolution modes: - Low res: 320×200 (NTSC) / 320×256 (PAL) — 3.58 MHz pixel clock - High res: 640×200 / 640×256 — 7.16 MHz pixel clock - Interlaced: doubles vertical resolution (400/512 lines) - Hires + interlaced: 640×400 / 640×512

On AGA, all 8 bitplanes are available in every resolution — provided the memory architecture can supply the bandwidth (fetch modes, see AGA). AGA dual playfield allows 4+4 bitplanes in all resolutions.

The Amiga supports dual playfield mode — two independent playfields (PF1 in front, PF2 behind) with independent color depths and scroll positions. Each playfield can scroll independently via scroll registers.

Audio

Paula provides four independent DMA-driven audio channels:

Feature Value
Channels 4 (two per stereo side)
Resolution 8-bit signed samples (-128 to +127)
Sample rate Programmable per channel (up to ~28 kHz NTSC / ~29 kHz PAL)
Volume 64 levels (0-63), independently programmable per channel
Stereo routing Channels 1+2 → left, Channels 0+3 → right

Audio data is fetched via DMA from Chip RAM. Each channel has its own programmable period (sample rate), volume, and data pointer. Once started, audio plays autonomously without CPU intervention.

DMA channel priority

The Amiga's memory bus is shared between the CPU and 25+ DMA channels. Priority is fixed by hardware:

  1. Refresh (DRAM refresh — always highest)
  2. Disk (floppy/hard disk DMA)
  3. Audio (4 channels)
  4. Sprites (8 channels)
  5. Bitplanes (display refresh)
  6. Copper
  7. Blitter
  8. 680x0 CPU (lowest priority)

Even-numbered memory cycles are used by audio, disk, refresh, and sprites. The Copper uses odd-numbered cycles. The Blitter and CPU compete for whatever remains. In high-resolution display modes with many bitplanes active, DMA traffic can consume most of the bandwidth, leaving little for the CPU — this is the famous "chip RAM bottleneck."

8520 CIA chips

Two Complex Interface Adapter (CIA) chips handle I/O:

CIA Name Functions
CIA A (8520) ciab.resource Floppy disk control, parallel port, keyboard input
CIA B (8520) cia.resource Serial port RTS/DTR, disk select, LED, mouse/joystick buttons

Each CIA contains: - Timer A and Timer B — 16-bit countdown timers (used by timer.device and for software-generated vertical blank interrupts) - TOD (Time of Day) clock — a 24-hour alarm clock driven by the 50/60 Hz power line or VBLANK - Serial shift register — used for keyboard data reception (CIA A) - I/O ports — 8-bit bidirectional ports for parallel I/O

ECS (Enhanced Chip Set)

The ECS chips (found in later A500/A2000/A3000) add: - Fat Agnus (8372A) — up to 2 MB Chip RAM, supports both NTSC and PAL on one chip - Super Denise (8373) — new scan-doubling, VGA-compatible modes, ECS register extensions - New registers for variable-resolution displays (FMode, BeamCon0) - ECS is backwards compatible with OCS at the register level

AGA (Advanced Architecture)

AGA (Advanced Amiga Architecture, internally AA — the third chip set generation after OCS and ECS) shipped in the A1200, A4000, and CD32 (1992–1994). The display chip is Lisa (successor to Denise), the DMA chip is Alice (successor to Agnus); Paula is unchanged. AGA is register-compatible with OCS/ECS at boot — everything below is opt-in via the new registers (BPLCON3, BPLCON4, CLXCON2, DIWHIGH, FMODE), all of which reset to safe defaults.

Bandwidth and fetch modes

Lisa's data path to Chip RAM is 32 bits wide (vs 16 on OCS/ECS), doubling display bandwidth; FAST page mode RAM doubles it again. The same enhancements apply to sprite fetches. Fetch width is controlled per-surface by two bits in the new FMODE register: BPAGEM (page mode) and BPL32 (32-bit fetch) for bitplanes, SPAGEM and SPR32 for sprites — sprite/biplane data can be fetched 16, 32, or 64 bits wide. For sprites, fetch width sets on-screen width: 32-bit fetch → 32-pixel sprites; 64-bit fetch (32-bit + FAST page mode double) → 64-pixel sprites — vs 16 pixels with the standard 16-bit OCS/ECS fetch. AGA only.

8 bitplanes, 256 colors

Eight bitplanes in all resolutions where bandwidth allows (ECS capped at 6):

Mode Bitplanes Colors
Single playfield up to 8 256 from palette
Dual playfield 4+4 16 + 16 (each playfield offset into palette)
HAM8 8 262,144 displayed / 16,777,216 palette
EHB 6 64 (kept for compatibility only)

BPLCON4 (bits 15–8) holds an 8-bit mask XORed onto the bitplane address — the Copper can swap the whole color map with one MOVE. BPLCON3 PF2OF2-0 gives the second playfield its own offset into the color table (needed now that DPF playfields can be 4 bitplanes deep).

HAM8

The new 8-bitplane HAM (Hold and Modify) mode is enabled by setting the BPU field in BPLCON0 to 8 with HAMEN set. Bitplanes 1–2 are control bits (analogous to bitplanes 5–6 in 6-bitplane HAM): 00 loads a new base register (1 of 64), 01 modifies blue, 10 modifies red, 11 modifies green. The 6 modify bitplanes feed the 6 MSBs of each gun — the 2 LSBs stay unmodified, so with well-chosen base registers a single HAM8 screen can show all 16,777,216 colors. HAM (6 and 8) works in all resolutions, not just LORES. EHB survives for compatibility (SHRES=HIRES=HAMEN=DPF=0, BPU=6; disabled by KILLEHB in BPLCON2 since ECS).

256×25-bit palette

The color table grows from 32×12-bit to 256 entries, 25 bits wide (8R + 8G + 8B + 1 genlock bit). Loading still goes through 32 register addresses: LOCT (BPLCON3) selects loading the 16 MSBs or LSBs (loading MSB also loads LSB — for 24-bit color, write LSB after MSB), and BANK2-0 select one of 8 banks of 32 entries (COLOR00–1F through E0–FF). RDRAM (BPLCON2) turns color writes into reads. No more "scrambling" of SHRES color entries — the ECS-era artifice is gone.

Sprites

  • Resolution selectable via SPRES1-0 (BPLCON3): LORES, HIRES or SHRES, independently of bitplane resolution; attached sprites work in all resolutions
  • Wider sprites via fetch mode: 32 pixels with 32-bit fetch (SPR32), 64 pixels with 64-bit fetch (SPR32+SPAGEM) — vs 16 pixels on OCS/ECS
  • BRDRSPRT shows sprites in the display border
  • OSPRM/ESPRM 4-bit mask fields relocate the odd/even sprite color maps (odd is used for attached sprites)
  • SSCAN2 (FMODE) scan-doubles sprites: per-sprite via each SPRxPOS bit 10; when off, Lisa reuses the previous line's data — only position/control registers need rewriting. Sprite vertical start/stop must have matching parity

Scan-doubling (15 kHz → 31 kHz)

BSCAN2 (FMODE) scan-doubles bitplanes so 15 kHz screens can share a 31 kHz display. When enabled, odd and even bitplanes share one modulus register per line (selected by comparing DIWSTRT bit V0 with the beam counter) — so dual-playfield screens generally won't display correctly scan-doubled.

Comparators, collision, genlock

  • All programmable horizontal comparators (DIWHIGH, HBSTOP, SPRCTL, BPLCON1) get 35 ns resolution (1 SHRES pixel); BPLCON1 scroll fields grow to 8 bits per playfield (scroll granularity 35 ns, up to 32 bus cycles of delay). The 140 ns weight moved to the 3rd LSB — ECS's PF1H0 is now named PF1H2
  • CLXCON2 adds enable/match bits for bitplanes 7–8 (ENBP7/ENBP6, MVBP7/MVBP8); CLXDAT unchanged
  • ECS genlock features carry over to Lisa: ZDBPEN/ZDBPSEL (bitplane transparency mask on ZD pin), ZDCTEN (per-color genlock bit), ZDCLKEN (14 MHz video-synced clock), BRDNTRAN (opaque border for framing live video)

Compatibility notes

  • The new RST input resets all AA-era register bits
  • ECSENA (BPLCON3) forces BRDRBLNK, BRDNTRAN, ZDCLKEN, EXTBLKEN, BRDRSPRT low, so old copper lists keep working
  • Writing CLXCON resets CLXCON2; writing DIWSTRT/DIWSTOP resets DIWHIGH — inherited from ECS
  • 28 MHz pixel clock for clean HIRES/SHRES pixels; Alice's clock generator is synchronized from Lisa's 14 MHz/SCLK outputs (genlock XCLK/XCLKEN pins are gone — an external MUX is now required)

The OS-level counterpart (24-bit graphics.library API, SetRGB32, palette sharing, mode promotion) is covered in AA (Advanced Amiga) Graphics Features.

See Also

Sources: Commodore-Amiga, Inc., "Amiga Hardware Reference Manual" 3rd Edition (1992); AA chip set "New features for AA" summary (AGA guide, via iKod.se). Raw: raw/hardware/amiga-hardware-reference.md; raw/hardware/aga-new-features.md Updated: 2026-08-20