Zorro III Expansion Bus

Zorro III is the 32-bit autoconfiguring expansion bus designed by Dave Haynie for the Amiga 3000. It is a fully asynchronous, multiplexed bus that provides 32-bit address and data paths, burst-mode transfers, fair DMA arbitration, and vectored interrupts — while maintaining backwards compatibility with Zorro II. This article is compiled from the official Zorro III Bus specification (Rev 1.10, "Vernal Equinox Release," March 20, 1991).

Design rationale

Zorro II (the A2000 bus) was limited to 24-bit addressing (16 MB) and used 68000-style bus arbitration where a master held the bus as long as it wanted. For the A3000 with its 68030 and 32-bit address space, Commodore needed:

  • Full 32-bit address and data paths
  • Bus speed independent of CPU clock
  • Burst mode (multiple transfers per address phase)
  • Bus locking for multiprocessor hardware semaphores
  • Cache support signals
  • Fair, cycle-by-cycle arbitration
  • High-speed vectored interrupts

Bus architecture

Zorro III is fully asynchronous — no clock reference drives bus cycles. All events are controlled by handshaking strobes. The bus multiplexes address and data on the same 100-pin connector as Zorro II: A31-A8 are latched on the falling edge of /FCS (Full Cycle Strobe), while A2-A7 are non-multiplexed (available throughout the cycle).

Every cycle starts as a Zorro III cycle. If the address falls in Zorro II space, the bus controller inscribes a compatible Zorro II cycle automatically.

A3000 memory map

Address range Region
$00000000–$001FFFFF Chip memory (2 MB)
$00200000–$009FFFFF Zorro II memory expansion (8 MB)
$00E80000–$00EFFFFF Zorro II I/O expansion (AUTOCONFIG Z2)
$00F00000–$00FFFFFF A2000 motherboard register space
$08000000–$0FFFFFFF A3000 motherboard space
$10000000–$7FFFFFFF Zorro III 32-bit expansion (~1.75 GB)

Bus cycles

Simple (full) cycle

  1. Master asserts /FCS and drives address
  2. Address latched on falling edge of /FCS
  3. Master drives data (write) or tri-states (read)
  4. DOE (Data Operation Enable) asserted
  5. Master asserts /DSN (data strobe)
  6. Slave asserts /SLAVEN (acknowledging cycle) and /DTACK (data ready)
  7. Master reads/drives data, negates /DSN and /FCS

Multiple transfer (burst) cycle

Extends the full cycle for multiple 32-bit transfers within a 256-byte page (only A7-A2 change):

  1. Master asserts /MTCR with /FCS
  2. Slave acknowledges with /MTACK
  3. After the first transfer, the bus enters short cycles: master negates /DSN+/MTCR but holds /FCS+DOE; slave holds /SLAVEN
  4. A7-A2 change for each short cycle
  5. Slave negates /MTACK one short cycle ahead to signal end

Burst mode is highly recommended for memory boards.

Bus locking

For multiprocessor systems, /LOCK grants a PIC multiple atomic full cycles (hardware semaphore support). This prevents any other master from intervening between cycles.

Arbitration

Zorro III introduces fair, cycle-by-cycle arbitration:

  • A PIC (Processor Independent Controller) registers by toggling /BRN on the rising edge of 7M
  • The bus controller grants one full cycle at a time via /BGN
  • The CPU is always scheduled alongside PICs
  • Load balancing distributes bus time among all registered masters
  • /BCLR (Bus Clear) signals a pending bus request so the current master should wrap up

Zorro II masters use 68000-style arbitration (/BR, /BG, /BGACK); the bus controller bridges them.

Quick interrupts

Zorro III adds Quick Interrupts: the interrupting PIC supplies its own 8-bit vector on D0-D7, arbitrated in hardware:

  1. PIC asserts its interrupt level (/INT2 or /INT6)
  2. Bus controller initiates polling phase: all interrupting PICs assert /SLAVEN
  3. Vector phase: bus controller selects one PIC, which drives the vector + /DTACK
  4. Auto-vector timeout fallback ensures Zorro II compatibility

Only /INT2 and /INT6 are currently defined; all others reserved.

AUTOCONFIG

Configuration is a daisy-chain (/CFGIN → /CFGOUT, slot 0 to last). Unconfigured boards respond to a 64K configuration space:

Bus type Config space Cycle type
Zorro II $00E80000 16-bit
Zorro III $FF000000 32-bit

Key registers (read from AUTOCONFIG ROM)

Offset Register Purpose
$00 er_Type Bits 7-6 = Zorro III (10) or Zorro II (11); bits 2-0 = size code
$04 er_Product Product ID
$08 er_Flags Bit 7 = memory vs I/O; bit 6 = can't-be-shut-up; bit 5 = size extension
$10 er_Manufacturer Manufacturer ID
$18 er_SerialNumber 32-bit serial
$28 er_InitDiagVec Diagnostic vector

Size encoding: base codes 000-111 give 64 KB to 8 MB. With the extended bit (reg 08, bit 5), sizes up to 1 GB are possible.

After reading, the OS writes the base address to the board's config space to "place" it, then sets the "shut up" bit so the next board in the daisy chain becomes visible.

Timing

Timing is specified in nanosecond-level setup/hold requirements (not clock cycles):

Parameter Min Description
TFRS 15 ns Address setup to /FCS
TSLV 25 ns max /FCS to /SLAVEN delay
TDOE 30 ns min /FCS to DOE delay
TDS 10 ns min DOE to /DSN delay
TRDS 0 ns Data setup to /DTACK

PICs must use F-Series/ACT-Series TTL, fast PALs, or custom silicon — LS TTL won't meet specs.

Electrical and mechanical

  • Same 100-pin connector as Zorro II
  • Per-PIC power: +5V @ 2.0A, -5V @ 60mA, +12V @ 500mA, -12V @ 60mA
  • Three PIC variants: basic Zorro III, with ISA option, with Video option

See Also

Sources: Dave Haynie / Commodore-Amiga, Inc., "Zorro III Bus specification" Rev 1.10 (March 20, 1991). Raw: raw/hardware/zorro3-bus.md Updated: 2026-08-08