Gayle Chip Registers

The Gayle chip (Commodore part number 5719 / 390914-01) is the bus-controller IC that integrates IDE, PCMCIA, and miscellaneous control glue on the Amiga 600 and Amiga 1200 (introduced 1991–1992). On the A1200 it is paired with the A1200 IDE controller (registers in [$DA0000-$DA301F] range — see at-ide.md).

This page documents the complete Gayle register set as known from public Amiga hardware documentation (including the full PCMCIA-related bit definitions and memory windows). The CCIDE extended mode (A1200-only configurable IDE timing) is not documented here.

Register map (offsets from $DA8000)

Offset Absolute Name Access Description
$0000 $DA8000 gaylestatus R Status register (PCMCIA card status + IDE IRQ)
$1000 $DA9000 gaylechange R + clear-on-W Change-detect latches (PCMCIA status changes)
$2000 $DAA000 gayleint RW Interrupt enables + level control
$3000 $DAB000 gaylecontrol RW Memory speed + programming voltage
Address Name Access Description
$DE1000 gayleregid RW Chip version ID register
$A40000 gaylehedley — Auxiliary control register ("Hedley" — see below)

ID register ($DE1000)

The version ID is read with a specific sequence:

  • The register must be accessed only from a task context with FORBID (or DISABLE) surrounding the access.
  • The procedure is: write anything to the register, then read 8 successive times. The high bit (bit 7) of each read is the data — yielding one bit per read.
  • The expected pattern is 1-1-0-1-0-0-0-0 = $D0 = %11010000.
  • The first 4 bits indicate GAYLE VERSION; the last 4 bits indicate GAYLE REVISION. All REVISIONS are backward-compatible with earlier versions (if any).
BITDEF  GAYLE,ID,7          ; ID bit (in each read)
GAYLE_ID  EQU  %11010000

Status register ($DA8000)

Read-only.

Bit Define Meaning
7 GAYLEB_STATUS_IDEINT IDE interface interrupt pending
6 GAYLEB_STATUS_CCDET PCMCIA card-detect changed
5 GAYLEB_STATUS_BVD1 / GAYLEB_STATUS_SC Battery voltage detect 1 / Status change
4 GAYLEB_STATUS_BVD2 / GAYLEB_STATUS_DA Battery voltage detect 2 / Digital audio
3 GAYLEB_STATUS_WR Write-protect status
2 GAYLEB_STATUS_BSYIRQ Busy / IRQ status
1 GAYLEB_STATUS_DIGAUDIO Digital audio enable status
0 GAYLEB_STATUS_CCDISABLE Card-disable status

Change-detect register ($DA9000)

Read + clear-on-write. Bits 7–2 share positions with the status register; bits 1–0 are distinct.

Bit Define Meaning
7 GAYLEB_CHANGE_IDEINT IDE interrupt change
6 GAYLEB_CHANGE_CCDET Card-detect change (latched)
5 GAYLEB_CHANGE_BVD1 / GAYLEB_CHANGE_SC BVD1 / Status change (latched)
4 GAYLEB_CHANGE_BVD2 / GAYLEB_CHANGE_DA BVD2 / Digital audio change (latched)
3 GAYLEB_CHANGE_WR Write-protect change (latched)
2 GAYLEB_CHANGE_BSYIRQ Busy / IRQ change (latched)
1 GAYLEB_DETRESET Hardware reset on card-detect
0 GAYLEB_DETBERR Bus error on card-detect

Writing the value read back into the register clears the latched bits.

Interrupt control register ($DAA000)

Read/write.

Bit Define Meaning
7 GAYLEB_INT_IDEINT Enable IDE interrupt
6 GAYLEB_INT_CCDET Enable card-detect interrupt
5 GAYLEB_INT_BVD1 / GAYLEB_INT_SC Enable BVD1 / Status-change interrupt
4 GAYLEB_INT_BVD2 / GAYLEB_INT_DA Enable BVD2 / Digital-audio interrupt
3 GAYLEB_INT_WR Enable write-protect interrupt
2 GAYLEB_INT_BSYIRQ Enable Busy/IRQ interrupt
1 GAYLEB_LEVEL_BVD / GAYLEB_LEVEL_DA / GAYLEB_LEVEL_SC Interrupt level control (BVD/DA/SC)
0 GAYLEB_LEVEL_BSYIRQ Interrupt level control (BSY/IRQ)

Control register ($DAB000)

Read/write.

Bit Define Meaning
3 GAYLEB_MEMORY_SPEED1 Memory speed bit 1
2 GAYLEB_MEMORY_SPEED0 Memory speed bit 0
1 GAYLEB_PROGRAM_12V Apply 12 V programming voltage
0 GAYLEB_PROGRAM_5V Apply 5 V programming voltage

Memory speed control

The two MEMORY_SPEED bits select the PCMCIA memory access timing. The standard speed grades are:

Speed setting Memory speed bits Constant
250 ns (default) 00 CARD_SPEED_250NS
150 ns 01 (bit 0 set) CARD_SPEED_150NS
100 ns 10 (bit 1 set) CARD_SPEED_100NS
720 ns 11 (both bits set) CARD_SPEED_720NS 
CARD_SPEED_250NS  EQU  0                                       ; default
CARD_SPEED_150NS  EQU  GAYLEF_MEMORY_SPEED0
CARD_SPEED_100NS  EQU  GAYLEF_MEMORY_SPEED1
CARD_SPEED_720NS  EQU  GAYLEF_MEMORY_SPEED0!GAYLEF_MEMORY_SPEED1

"Hedley" register ($A40000)

The Gayle chip exposes an additional auxiliary control register at $A40000, named gaylehedley in the public hardware headers. It is used by the built-in card driver for a hardware-specific setup that depends on the Gayle revision.

PCMCIA memory windows

The PCMCIA card slot memory is mapped into the Amiga address space in four windows:

Window Address Size Purpose
COMMON_MEMORY $600000 4 MB (COMMON_MEM_SIZE = $400000) PCMCIA common memory
ATTRIBUTE_MEMORY $A00000 128 KB (ATTR_MEM_SIZE = $020000) PCMCIA attribute memory (CIS, config registers)
IO_MEMORY $A20000 128 KB (IO_MEM_SIZE = $020000) PCMCIA I/O space
FLASH_ROM $A40000 — Flash ROM region (overlaps gaylehedley)

Reset sequence (canonical card.resource initialization)

The standard reset for the four Gayle registers is performed by writing known values to clear change latches and reset the interrupt and control state:

  1. Clear change latches — write IDE_MASK!CC_MASK to gaylechange (clears all status change interrupts except IDE and CC_DET, also clears RESET and BERR bits).
  2. Clear status register — write $00 to gaylestatus (clears CC_DET, WR, BVD1, BVD2, IRQ, DIG_AUD, CC_DISABLE).
  3. Reset control register — write $00 to gaylecontrol (default memory speed 250 ns, default programming voltage).
  4. Reset interrupt enables — clear GAYLEB_INT_BVD2, then set GAYLEF_INT_BVD1!GAYLEF_INT_WR!GAYLEF_INT_BSYIRQ (the default enabled set: BVD1, WR, BSY/IRQ).

After this sequence, the chip is in a known idle state ready for the next card insertion.

Interrupt vector registration

GAYLE_ADDR ($DA8000) is registered as the interrupt vector address — when the interrupt fires, the CPU reads the vector from this location. Gayle's INT line drives the interrupt acknowledge cycle, and the interrupt code pointer points to this base.

Limitations

This page covers the four main registers ($DA8000+offsets) plus the ID register ($DE1000) and the Hedley auxiliary register ($A40000). The CCIDE register space (configurable IDE timing modes — A1200-only feature) is not documented here.

Cross-references