MC68040 and MC68060 Architecture¶

The MC68040 (1990) and MC68060 (1994) are the fourth- and sixth-generation members of the M68000 family. Both are user object-code compatible with every earlier 68000-family processor, yet they represent the two largest architectural leaps in the family: the 040 integrated the FPU, paged MMU, and large caches onto one die for the first time; the 060 became a superscalar processor that issues two integer instructions per clock. The MC68040 powered the Amiga 4000; the MC68060 was the CPU of choice for the highest-performance Amiga accelerator cards (Phase5, Blizzard, CyberStorm).

Family comparison¶

Feature	MC68030	MC68040	MC68060
Generation	3rd	4th ("third generation")	6th
Process	HCMOS	HCMOS	HCMOS (2.5M transistors)
Integer unit	Single pipeline	6-stage pipeline	Dual 4-stage pipelines (superscalar)
FPU	External (68881/68882)	On-chip, MC68881/68882-compatible	On-chip, MC68040- and MC68881/68882-compatible
MMU	On-chip paged (single)	Dual demand-paged (instruction + data)	Dual demand-paged (MC68040-compatible)
ATCs	22-entry	Dual (instruction + data)	Dual 64-entry (instruction + data)
Instruction cache	256 bytes	4 Kbytes	8 Kbytes
Data cache	256 bytes	4 Kbytes	8 Kbytes
Branch handling	Static	Shadow-pipeline prefetch	256-entry branch cache (zero-cycle branches)
Bus	Asynchronous, burst	32-bit nonmultiplexed synchronous	32-bit synchronous, high-bandwidth
Cache coherency	—	On-chip bus snoop logic	On-chip bus snoop logic
Peak throughput	Single-issue	Concurrent IU/FPU/MMU/bus	>100 MIPS @ 66 MHz
vs 68040	—	1.0	1.6-1.7x at same clock; 3.2-3.4x vs 25 MHz 68040

Sources: mc68040um.md (1.2 Features, 1.4 Functional Blocks); mc68060um.md (1.2 Features, 1.3 Architecture).

MC68040 (1990)¶

The M68040 family (MC68040, MC68040V, MC68LC040, MC68EC040, MC68EC040V) integrates an MC68030-compatible integer unit (IU), two independent caches, and (on the full MC68040) an MC68881/MC68882-compatible floating-point unit and dual independent demand-paged memory management units. It uses multiple independent execution pipelines, multiple internal buses, and a full internal Harvard architecture with separate physical caches for instruction and data accesses. On-chip bus snoop logic directly supports cache coherency in multimaster applications.

Six-stage integer pipeline¶

The MC68040 IU pipeline consists of six stages:

Instruction Fetch — fetching an instruction from memory.
Decode — converting an instruction into micro-instructions.
<ea> Calculate — if the instruction references memory, calculate its effective address.
<ea> Fetch — data is fetched from memory.
Execute — the data is manipulated.
Write-Back — the result is written to on-chip caches or external memory.

The pipeline contains shadow registers that begin processing future instructions for conditional branches while the main pipeline processes current ones: both execution paths of a branch are fetched and decoded to minimize refilling the pipeline. The <ea> calculate stage was added over the MC68030 to eliminate pipeline blockage for postincrement/predecrement/immediate-add addressing-mode updates.

On-chip FPU and MMU¶

FPU — MC68881/MC68882-compatible and ANSI/IEEE 754 compliant. Optimized to execute the most commonly used subset of the 68881/68882 instruction set in hardware (with single- and double-precision rounding). Instructions not directly supported in hardware are emulated in software by the M68040FPSP (Floating-Point Software Package). The FPU runs concurrently with the IU, MMU, and bus controller, maximizing throughput.
MMU — dual, independent, demand-paged memory management units, one for instruction accesses and one for data accesses. Both support 4-Gbyte direct addressing range.

Caches and bus¶

The MC68040 has simultaneously accessible 4-Kbyte physical instruction cache and 4-Kbyte physical data cache. A 32-bit, nonmultiplexed external address and data bus with a synchronous interface provides low-latency bus accesses to reduce the cache-miss penalty.

The MOVE16 instruction¶

MOVE16 is new to the M68040 instruction set, supporting efficient 16-byte (128-bit) memory-to-memory data transfers. It uses line transfers and remains present on the 68060.

MC68040 variants¶

Device	FPU	MMU	Notes
MC68040	Yes	Yes (dual)	Full part
MC68040V	No	Yes	3.3 V static, operates down to 0 MHz; low-power stop mode
MC68LC040	No	Yes	Pin compatible with MC68040
MC68EC040	No	No (ACU)	Embedded control; access control unit replaces MMU
MC68EC040V	No	No (ACU)	3.3 V static embedded variant

The MC68EC040 retains four transparent translation registers (usable for cache modes and protection) but cannot perform table-walk page translation.

MC68060 (1994)¶

The MC68060 is a superscalar processor — the most advanced member of the M68000 family. It incorporates 2.5 million transistors and offers superscalar integer performance of over 100 MIPS at 66 MHz. It delivers 1.6-1.7 times the MC68040 performance at the same clock rate, and 3.2-3.4 times the performance of a 25 MHz MC68040.

Superscalar dual-pipeline design¶

The MC68060 employs a deep pipeline, dual-issue superscalar execution architecture. It allows simultaneous execution of two integer instructions (or one integer and one floating-point instruction) and one branch instruction during each clock. The dual operand execution pipelines (OEPs) — named primary (pOEP) and secondary (sOEP) — are four-stage pipelines that operate in lock-step mode: instructions execute simultaneously but not out-of-order, so the architecture is software-invisible. The net effect is sustained execution rates of less than one machine cycle per instruction.

The pipeline is split into two decoupled halves:

Instruction Fetch Unit (IFU) — a four-stage prefetch pipeline. It contains a 64-entry instruction ATC (4-way set-associative), an 8-Kbyte 4-way physically-mapped instruction cache, the branch cache, and a 96-byte FIFO instruction buffer that decouples fetching from execution. Variable-length M68000 instructions are internally decoded into a fixed-length representation before dispatch to the OEPs.
Operand Execution Pipelines (OEP) — dual four-stage RISC execution engines sharing a register file (RGF). Each has a 64-entry operand data ATC (4-way). The 8-Kbyte data cache is organized in a banked structure to allow simultaneous read and write access each clock. Most integer instructions execute in a single machine cycle. A four-entry store buffer and one-entry push buffer decouple the pipeline from external memory.

Branch cache and zero-cycle branches¶

The MC68060 introduces a 256-entry, 4-way set-associative, virtually-mapped branch cache that predicts branch direction based on past execution history. Using a technique called branch folding, the branch cache lets the instruction fetch pipeline detect and redirect the prefetch stream before the change of flow reaches the execution engines. As a result, most branches execute in zero cycles, minimizing pipeline refills.

Caches, MMU, and FPU¶

Dual 8-Kbyte caches — separate 8-Kbyte instruction and 8-Kbyte data caches, both 4-way set-associative and physically-mapped. Either cache can be frozen to prevent allocation over time-critical code or data. The full internal Harvard architecture supports concurrent instruction fetch, operand read, and operand write references on every clock.
MMU — MC68040-compatible paged memory management unit with dual 64-entry address translation caches (instruction and data). Present only on the MC68060 and MC68LC060.
FPU — IEEE-standard, MC68040- and MC68881/MC68882-compatible. Some instructions and data types are emulated in software by the MC68060FPSP.

Power management¶

The MC68060 is a fully-static design with dynamic power management and low-voltage operation. It automatically powers down internal functional blocks that are not needed on a clock-by-clock basis, and it directly interfaces to both 3 V and 5 V peripherals and logic.

MC68060 variants¶

Device	FPU	MMU	Notes
MC68060	Yes	Yes (dual 64-entry ATC)	Full part
MC68LC060	No	Yes	100% pin compatible with MC68060
MC68EC060	No	No	Transparent translation registers still usable for cache/protection

Dropped instructions and software emulation¶

To make the dual-pipeline superscalar design possible, the MC68060 removed several complex integer instructions from hardware. When the processor decodes one of these, it takes an unimplemented integer instruction exception (vector 61) so the OS can emulate it in software:

MULx producing a 64-bit product (MULS.L/MULU.L 32x32 -> 64)
DIVx using a 64-bit dividend (DIVS.L/DIVU.L 64/32)
CAS2 (compare-and-swap dual)
CHK2 / CMP2 (bounds check / compare)
CAS with a misaligned operand
MOVEP (move peripheral)

Emulation is provided by the MC68060ISP (Integer Software Package, exception handler) and MC68060ILSP (Integer Library Software Package). Floating-point instructions not implemented in hardware are emulated by the MC68060FPSP. This emulation requirement is directly relevant to the Amiga: accelerator-card drivers ship a 68060.library that installs these emulation vectors, without which software using the dropped instructions would crash. MOVE16 and CAS (aligned) remain implemented in hardware.

Relevance to the Amiga¶

Amiga model / card	CPU	Notes
A4000	MC68040 (25 MHz)	Full 040 with FPU + MMU; some low-cost units shipped with MC68EC040
A4000 accelerators	MC68040 (25/40 MHz)	Common upgrade path
Phase5 CyberStorm/Blizzard	MC68060 (50/66 MHz)	Highest-performance classic Amiga CPUs; require 68060.library for dropped-instruction emulation
Blizzard 1260	MC68060 (50 MHz)	A1200 accelerator

The 68040's on-chip FPU and dual MMUs made it the natural CPU for the A4000's multimedia and computing workloads. The 68060's superscalar design and zero-cycle branches gave accelerator-equipped Amigas performance several times that of a stock 68040 system, but the dropped integer instructions meant correct operation depended on the OS loading the integer/floating-point emulation libraries. The 68060's on-chip paged MMU is also the hardware basis for advanced Amiga memory-protection and debugging tools (Enforcer, mmu.library).

Keys	Action
`?`	Open this help
`n`	Next page
`p`	Previous page
`s`	Search