680x0 Instruction Reference

The Motorola 68000 family was designed for strong upward object-code compatibility, but compatibility is not absolute. Examples include the MC68010 privilege change for MOVE from SR, the removal of CALLM/RTM after the MC68020, MMU programming-model changes, and MC68060 instructions that require exception-driven software support. This article is a master instruction matrix crossing the instruction groups documented here against each CPU generation. Use it to determine which opcode is available on which target when writing assembly for the Amiga family (A500/A1000 = 68000; A1200 = 68020; A3000/A4000 = 68030/68040).

This article is populated progressively from the official Motorola User's Manuals (MC68000UM, MC68010UM, MC68020UM, MC68030UM, MC68040UM, MC68060UM). The 68000 column is the source of truth (verified against MC68000UM Table 2-2, Instruction Set Summary). The 68020 column is verified against MC68020UM Table 1-2 (Instruction Set). The 68030 column is verified against MC68030UM Table 1-2 (Instruction Set) + Section 1.7 (MMU). The 68040 column is verified against MC68040UM Table 1-4. The 68060 column is verified against MC68060UM Table 1-3, Appendix C.2, and Section 6.5.1. The other CPU columns are filled in incrementally as each reference manual is processed.

Contents

How to read the table

  • ✅ — native: instruction is implemented in CPU silicon
  • ⚠ — trap/software-support: the encoding is recognized as a compatibility case but is not completed in hardware; the CPU raises the documented exception and software may emulate it if the required support package/handler is installed
  • ❌ — unsupported: instruction is not part of this CPU's ISA
  • ❓ — to be confirmed against the official manual (manual not yet processed)
  • italics — instruction exists with restricted semantics (e.g. supervisor-only, mode-dependent, dropped/replaced on a later CPU)

680x0 instruction matrix

The matrix below crosses the documented instructions against each CPU generation. ✅ = native, ⚠ = requires the documented exception/software-support path, ❌ = unsupported/not part of that processor's implemented ISA, ❓ = not yet verified. The 68060 Pipe column applies to the 68060 only and indicates which Operand Execution Pipeline (per MC68060UM §10, Superscalar Classification):

  • pOEP-only — primary OEP, blocks the secondary (no dual-issue)
  • pOEP | sOEP — eligible for dual-issue (parallel dispatch in both pipelines)
  • pOEP-until-last — runs on pOEP but locks the sOEP until completion
  • pOEP-but-allows-sOEP — typically FPU (parallel integer execution allowed)
  • For 68000/68010/68020/68030/68040: pipe column is — (no superscalar)

See Clock cycle counts below for per-CPU execution timing.

Data movement

Mnemonic Operation 68000 68010 68020 68030 68040 68060 68060 Pipe
EXG Exchange registers ✅ ✅ ✅ ✅ ✅ ✅ pOEP-only
LEA Load effective address ✅ ✅ ✅ ✅ ✅ ✅ pOEP | sOEP
LINK Link stack ✅ ✅ ✅ ✅ ✅ ✅ pOEP-until-last
MOVE Move (R→R baseline) ✅ ✅ ✅ ✅ ✅ ✅ pOEP | sOEP
MOVEA Move address ✅ ✅ ✅ ✅ ✅ ✅ pOEP | sOEP
MOVE from CCR Read CCR (68010+) ❌ ✅ ✅ ✅ ✅ ✅ pOEP-only
MOVE to CCR Write CCR ✅ ✅ ✅ ✅ ✅ ✅ pOEP | sOEP
MOVE from SR Read SR (privileged on 68010+) ✅* ✅ ✅ ✅ ✅ ✅ pOEP-only
MOVE to SR Write SR (supervisor) ✅ ✅ ✅ ✅ ✅ ✅ pOEP-only
MOVE USP Move user stack pointer (supervisor) ✅ ✅ ✅ ✅ ✅ ✅ pOEP-only
MOVEC Move control register (supervisor) ❌ ✅ ✅ ✅ ✅ ✅ pOEP-only
MOVEM Move multiple registers ✅ ✅ ✅ ✅ ✅ ✅ pOEP-only
MOVEP Move peripheral data ✅ ✅ ✅ ✅ ✅ ⚠ (emulated)
MOVEQ Move quick (immediate) ✅ ✅ ✅ ✅ ✅ ✅ pOEP | sOEP
MOVES Move with alternate function code (supervisor) ❌ ✅ ✅ ✅ ✅ ✅ pOEP-only
MOVE16 16-byte block move (16-byte aligned; register postincrement and absolute-long forms) ❌ ❌ ❌ ❌ ✅ ✅ pOEP-only
PEA Push effective address ✅ ✅ ✅ ✅ ✅ ✅ pOEP-only
SWAP Swap register halves ✅ ✅ ✅ ✅ ✅ ✅ pOEP | sOEP
UNLK Unlink stack ✅ ✅ ✅ ✅ ✅ ✅ pOEP-only

Integer arithmetic

Mnemonic Operation 68000 68010 68020 68030 68040 68060 68060 Pipe
ABCD Add decimal with extend ✅ ✅ ✅ ✅ ✅ ✅ pOEP-only
ADD Add binary ✅ ✅ ✅ ✅ ✅ ✅ pOEP | sOEP
ADDA Add address ✅ ✅ ✅ ✅ ✅ ✅ pOEP | sOEP
ADDI Add immediate ✅ ✅ ✅ ✅ ✅ ✅ pOEP | sOEP
ADDQ Add quick ✅ ✅ ✅ ✅ ✅ ✅ pOEP | sOEP
ADDX Add extended ✅ ✅ ✅ ✅ ✅ ✅ pOEP-only
CLR Clear operand ✅ ✅ ✅ ✅ ✅ ✅ pOEP | sOEP
CMP Compare ✅ ✅ ✅ ✅ ✅ ✅ pOEP | sOEP
CMPA Compare address ✅ ✅ ✅ ✅ ✅ ✅ pOEP | sOEP
CMPI Compare immediate ✅ ✅ ✅ ✅ ✅ ✅ pOEP | sOEP
CMPM Compare memory ✅ ✅ ✅ ✅ ✅ ✅ pOEP | sOEP
CMP2 Compare against bounds, set cc (68020+; emulated on 68060) ❌ ❌ ✅ ✅ ✅ ⚠ (emulated)
DIVS.W Signed divide 32÷16→16r:16q ✅ ✅ ✅ ✅ ✅ ✅ pOEP-only
DIVS.L Signed divide 32÷32→32q ❌ ❌ ✅ ✅ ✅ ✅ pOEP-only
DIVSL.L Signed divide 32÷32→32r:32q ❌ ❌ ✅ ✅ ✅ ✅ pOEP-only
DIVU.W Unsigned divide 32÷16→16r:16q ✅ ✅ ✅ ✅ ✅ ✅ pOEP-only
DIVU.L Unsigned divide 32÷32→32q ❌ ❌ ✅ ✅ ✅ ✅ pOEP-only
DIVUL.L Unsigned divide 32÷32→32r:32q ❌ ❌ ✅ ✅ ✅ ✅ pOEP-only
EXT.W Sign-extend byte→word ✅ ✅ ✅ ✅ ✅ ✅ pOEP | sOEP
EXT.L Sign-extend word→long ✅ ✅ ✅ ✅ ✅ ✅ pOEP | sOEP
EXTB.L Sign-extend byte→long ❌ ❌ ✅ ✅ ✅ ✅ pOEP | sOEP
MULS.W Signed multiply 16×16→32 ✅ ✅ ✅ ✅ ✅ ✅ pOEP-only
MULS.L Signed multiply 32×32→32 ❌ ❌ ✅ ✅ ✅ ✅ pOEP-only
MULS.L (wide) Signed multiply 32×32→64 (64-bit output, emulated on 68060) ❌ ❌ ✅ ✅ ✅ ⚠ (emulated)
MULU.W Unsigned multiply 16×16→32 ✅ ✅ ✅ ✅ ✅ ✅ pOEP-only
MULU.L Unsigned multiply 32×32→32 ❌ ❌ ✅ ✅ ✅ ✅ pOEP-only
MULU.L (wide) Unsigned multiply 32×32→64 (64-bit output, emulated on 68060) ❌ ❌ ✅ ✅ ✅ ⚠ (emulated)
NBCD Negate decimal with extend ✅ ✅ ✅ ✅ ✅ ✅ pOEP-only
NEG Negate ✅ ✅ ✅ ✅ ✅ ✅ pOEP | sOEP
NEGX Negate with extend ✅ ✅ ✅ ✅ ✅ ✅ pOEP-only
PACK Pack BCD (68020+; native on 68060) ❌ ❌ ✅ ✅ ✅ ✅ pOEP-only
SBCD Subtract decimal with extend ✅ ✅ ✅ ✅ ✅ ✅ pOEP-only
SUB Subtract binary ✅ ✅ ✅ ✅ ✅ ✅ pOEP | sOEP
SUBA Subtract address ✅ ✅ ✅ ✅ ✅ ✅ pOEP | sOEP
SUBI Subtract immediate ✅ ✅ ✅ ✅ ✅ ✅ pOEP | sOEP
SUBQ Subtract quick ✅ ✅ ✅ ✅ ✅ ✅ pOEP | sOEP
SUBX Subtract extended ✅ ✅ ✅ ✅ ✅ ✅ pOEP-only
TAS Test and set ✅ ✅ ✅ ✅ ✅ ✅ pOEP-only
TST Test ✅ ✅ ✅ ✅ ✅ ✅ pOEP | sOEP
UNPK Unpack BCD (68020+; native on 68060) ❌ ❌ ✅ ✅ ✅ ✅ pOEP-only

Logical and bit-field

Mnemonic Operation 68000 68010 68020 68030 68040 68060 68060 Pipe
AND Logical AND ✅ ✅ ✅ ✅ ✅ ✅ pOEP | sOEP
ANDI AND immediate ✅ ✅ ✅ ✅ ✅ ✅ pOEP | sOEP
ANDI to CCR AND immediate to CCR ✅ ✅ ✅ ✅ ✅ ✅ pOEP-only
ANDI to SR AND immediate to SR (supervisor) ✅ ✅ ✅ ✅ ✅ ✅ pOEP-only
BFCHG Test bit field and change (68020+) ❌ ❌ ✅ ✅ ✅ ✅ pOEP-only
BFCLR Test bit field and clear (68020+) ❌ ❌ ✅ ✅ ✅ ✅ pOEP-only
BFEXTS Extract bit field signed (68020+) ❌ ❌ ✅ ✅ ✅ ✅ pOEP-only
BFEXTU Extract bit field unsigned (68020+) ❌ ❌ ✅ ✅ ✅ ✅ pOEP-only
BFFFO Find first one in bit field (68020+) ❌ ❌ ✅ ✅ ✅ ✅ pOEP-only
BFINS Insert bit field (68020+) ❌ ❌ ✅ ✅ ✅ ✅ pOEP-only
BFSET Test bit field and set (68020+) ❌ ❌ ✅ ✅ ✅ ✅ pOEP-only
BFTST Test bit field (68020+) ❌ ❌ ✅ ✅ ✅ ✅ pOEP-only
EOR Exclusive OR ✅ ✅ ✅ ✅ ✅ ✅ pOEP | sOEP
EORI EOR immediate ✅ ✅ ✅ ✅ ✅ ✅ pOEP | sOEP
EORI to CCR EOR immediate to CCR ✅ ✅ ✅ ✅ ✅ ✅ pOEP-only
EORI to SR EOR immediate to SR (supervisor) ✅ ✅ ✅ ✅ ✅ ✅ pOEP-only
NOT Logical complement ✅ ✅ ✅ ✅ ✅ ✅ pOEP | sOEP
OR Logical OR ✅ ✅ ✅ ✅ ✅ ✅ pOEP | sOEP
ORI OR immediate ✅ ✅ ✅ ✅ ✅ ✅ pOEP | sOEP
ORI to CCR OR immediate to CCR ✅ ✅ ✅ ✅ ✅ ✅ pOEP-only
ORI to SR OR immediate to SR (supervisor) ✅ ✅ ✅ ✅ ✅ ✅ pOEP-only

Bit manipulation

Mnemonic Operation 68000 68010 68020 68030 68040 68060 68060 Pipe
BCHG Test bit and change ✅ ✅ ✅ ✅ ✅ ✅ pOEP | sOEP
BCLR Test bit and clear ✅ ✅ ✅ ✅ ✅ ✅ pOEP | sOEP
BSET Test bit and set ✅ ✅ ✅ ✅ ✅ ✅ pOEP | sOEP
BTST Test bit ✅ ✅ ✅ ✅ ✅ ✅ pOEP | sOEP

Shift and rotate

Mnemonic Operation 68000 68010 68020 68030 68040 68060 68060 Pipe
ASL / ASR Arithmetic shift left/right ✅ ✅ ✅ ✅ ✅ ✅ pOEP | sOEP
LSL / LSR Logical shift left/right ✅ ✅ ✅ ✅ ✅ ✅ pOEP | sOEP
ROL / ROR Rotate left/right (without X) ✅ ✅ ✅ ✅ ✅ ✅ pOEP | sOEP
ROXL / ROXR Rotate left/right with extend ✅ ✅ ✅ ✅ ✅ ✅ pOEP-only

Atomic memory operations (68020+)

Mnemonic Operation 68000 68010 68020 68030 68040 68060 68060 Pipe
CAS Compare-and-swap ❌ ❌ ✅ ✅ ✅ ✅ pOEP-only
CAS2 Compare-and-swap dual (68020+; emulated on 68060) ❌ ❌ ✅ ✅ ✅ ⚠ (emulated)

Program control

Mnemonic Operation 68000 68010 68020 68030 68040 68060 68060 Pipe
Bcc Branch conditionally ✅ ✅ ✅ ✅ ✅ ✅ pOEP-but-allows-sOEP¹
BRA Branch always ✅ ✅ ✅ ✅ ✅ ✅ pOEP-only
BSR Branch to subroutine ✅ ✅ ✅ ✅ ✅ ✅ pOEP-only
CALLM Call module (68020 only) ❌ ❌ ✅ ❌ ❌ ❌ (dropped)
DBcc Decrement and branch conditionally ✅ ✅ ✅ ✅ ✅ ✅ pOEP-but-allows-sOEP
JMP Jump ✅ ✅ ✅ ✅ ✅ ✅ pOEP-only
JSR Jump to subroutine ✅ ✅ ✅ ✅ ✅ ✅ pOEP-only
NOP No operation ✅ ✅ ✅ ✅ ✅ ✅ pOEP-only
RTD Return and deallocate (68010+) ❌ ✅ ✅ ✅ ✅ ✅ pOEP-only
RTM Return from module (68020 only) ❌ ❌ ✅ ❌ ❌ ❌ (dropped)
RTR Return and restore CCR ✅ ✅ ✅ ✅ ✅ ✅ pOEP-only
RTS Return from subroutine ✅ ✅ ✅ ✅ ✅ ✅ pOEP-only
TRAPcc Trap if condition (68020+; native on 68060, pOEP-only) ❌ ❌ ✅ ✅ ✅ ✅ pOEP-only

¹ A Bcc instruction is pOEP-but-allows-sOEP if it is not predicted from the branch cache AND the direction is forward OR if the Bcc is predicted as a "not-taken" branch. Predicted-taken Bcc instructions lock the sOEP until the branch resolves.

Range check (68020+)

Mnemonic Operation 68000 68010 68020 68030 68040 68060 68060 Pipe
CHK Check register against bounds ✅ ✅ ✅ ✅ ✅ ✅ pOEP-only
CHK2 Check register against bounds (68020+; emulated on 68060) ❌ ❌ ✅ ✅ ✅ ⚠ (emulated)

System control

Mnemonic Operation 68000 68010 68020 68030 68040 68060 68060 Pipe
ILLEGAL Illegal instruction trap ✅ ✅ ✅ ✅ ✅ ✅ pOEP | sOEP
RESET Assert RESET line (supervisor) ✅ ✅ ✅ ✅ ✅ ✅ pOEP-only
RTE Return from exception (supervisor) ✅ ✅ ✅ ✅ ✅ ✅ pOEP-only
STOP Stop and wait for interrupt (supervisor) ✅ ✅ ✅ ✅ ✅ ✅ pOEP-only
TRAP Trap instruction (vectored) ✅ ✅ ✅ ✅ ✅ ✅ pOEP | sOEP
TRAPV Trap on overflow ✅ ✅ ✅ ✅ ✅ ✅ pOEP-only
BKPT Breakpoint (68010+) ❌ ✅ ✅ ✅ ✅ ✅ pOEP-only

Cache and MMU control

Mnemonic Operation 68000 68010 68020 68030 68040 68060 68060 Pipe
CINV Invalidate cache lines (68040+) ❌ ❌ ❌ ❌ ✅ ✅ pOEP-only
CPUSH Push and invalidate cache lines (68040+) ❌ ❌ ❌ ❌ ✅ ✅ pOEP-only
PFLUSH Flush ATC entries (68030+; syntax/semantics differ by generation; native on full MC68060/MC68LC060) ❌ ❌ ❌ ✅ ✅ ✅ pOEP-only
PFLUSHA Flush all ATC entries (68030+; native on 68040/68060 per MC68060UM §4.7.2 + Table 10-24) ❌ ❌ ❌ ✅ ✅ ✅ pOEP-only
PLOAD (PLOADR/PLOADW) Load entry into ATC (68030+) ❌ ❌ ❌ ✅ ❌ ❌ pOEP-only
PMOVE Move to/from MMU registers (68030+) ❌ ❌ ❌ ✅ ❌ ❌ pOEP-only
PMOVEFD Move to/from MMU regs with flush-disable (68030+) ❌ ❌ ❌ ✅ ❌ ❌ pOEP-only
PTEST (PTESTR/PTESTW) Test a logical address (68030/68040; unimplemented on 68060, where PLPA is the processor-specific translation helper) ❌ ❌ ❌ ✅ ✅ ❌ pOEP-only
PLPA Load physical address / translation helper (68060 only) ❌ ❌ ❌ ❌ ❌ ✅ pOEP-only

Floating-point unit (FPU) — MC68881/68882 coprocessor on 68020/68030, integrated on 68040/68060

The FPU instruction set was defined by the MC68881 and MC68882. The MC68040 integrates a commonly used subset of that architecture in hardware; importantly, its native set includes conditional FP operations such as FBcc, FDBcc, FScc, and FTRAPcc, while functions such as FINT, FINTRZ, FGETEXP, FGETMAN, FMOD, FREM, FSCALE, FMOVECR, and the transcendental functions rely on AmigaOS CPU-support software such as 68040.library when software compatibility is required. The MC68060 implements a different hardware subset: several operations that are native on the 68040 (notably FDBcc, FScc, and FTRAPcc) are unimplemented on the 68060 and are handled on AmigaOS through CPU-support software such as 68060.library.

The 68882 is pin- and software-compatible with the 68881 and implements the same FPU instruction set (per MC68881/MC68882UM §1.4, verified against Table 8-2 vs Table 8-3). No instructions, monadic operations, dyadic operations, conditional mnemonics, or data formats are added by the 68882 — every instruction present on the 68882 is also present on the 68881 (with documented execution times in Table 8-2). The 68882 instead improves performance and concurrency:

  • Performance: higher throughput than the MC68881 through implementation improvements, including dedicated conversion hardware and lower coprocessor-interface overhead. Both the MC68881 and MC68882 use a 67-bit arithmetic unit/barrel-shifter architecture; the 67-bit datapath is not an MC68882-only change.
  • Concurrent execution of multiple FP instructions — only the 68882 can issue a new FP instruction before the previous one completes (UM §1, §8).
  • Special-purpose hardware for high-speed binary-real ↔ extended-precision conversion (UM §1).
  • State-frame extension for concurrent-execution context: the FSAVE/FRESTORE state frame includes MC68882-only bits for the operand-register validity map (per UM §7.2.4.4, "INTERNAL STATE INFORMATION (MC68882 ONLY)").
  • 8-bit peripheral mode documented more completely (the 68881 also supports it via the SIZE pin).

MC68881/MC68882 floating-point instruction set

The official combined MC68881/MC68882 documentation describes the shared floating-point ISA. The functional groups used here are five major classes:

  1. Moves (between 68882 and memory, or 68882 ↔ 68882): FMOVE.<fmt> <ea>,FPn / FMOVE.<fmt> FPm,<ea> / FMOVE.X FPm,FPn / FMOVEM <list>,<ea> (move multiple registers)
  2. Monadic operations (one operand → result in floating-point data register): 27 instructions — FABS, FACOS, FASIN, FATAN, FATANH, FCOS, FCOSH, FETOX, FETOXM1, FGETEXP, FGETMAN, FINT, FINTRZ, FLOG10, FLOG2, FLOGN, FLOGNP1, FNEG, FSIN, FSINCOS, FSINH, FSQRT, FTAN, FTANH, FTENTOX, FTST, FTWOTOX
  3. Dyadic operations (two operands → result in FPn): 10 instructions — FADD, FCMP, FDIV, FMOD, FMUL, FREM, FSCALE, FSGLDIV, FSGLMUL, FSUB
  4. Branch, set, and trap on condition: FBcc, FDBcc, FScc, FTRAPcc — each with 32 conditional test specifiers (F, EQ, OGT, OGE, OLT, OLE, OGL, OR, UN, UEQ, UGT, UGE, ULT, ULE, NE, T, SF, SEQ, GT, GE, LT, LE, GL, GLE, NGLE, NGL, NLE, NLT, NGE, NGT, SNE, ST)
  5. Miscellaneous / FPU control: FMOVE FPcr,<ea> / FMOVE <ea>,FPcr (control registers: FPCR, FPSR, FPIAR), FSAVE <ea>, FRESTORE <ea>

In the matrix below, the 68020/68030 columns apply to both the 68881 and the 68882 — the two coprocessors share the same instruction set per UM §1.4, so there are no 68882-only instructions to mark in the row labels.

Mnemonic Operation 68000 68010 68020 68030 68040 68060
FABS Absolute value ❌ ❌ ✅² ✅² ✅ ✅
FADD FP add ❌ ❌ ✅² ✅² ✅ ✅
FBcc FP branch conditionally ❌ ❌ ✅² ✅² ✅ ✅
FCMP FP compare ❌ ❌ ✅² ✅² ✅ ✅
FDBcc FP decrement and branch ❌ ❌ ✅² ✅² ✅ ⚠¹
FDIV FP divide ❌ ❌ ✅² ✅² ✅ ✅
FINT FP integer part (68881+ silicon; software-handled on AmigaOS/68040 via 68040.library) ❌ ❌ ✅² ✅² ⚠³ ✅
FINTRZ FP integer part, round-to-zero (68881+ silicon; software-handled on AmigaOS/68040 via 68040.library) ❌ ❌ ✅² ✅² ⚠³ ✅
FMOVE FP move (including to/from FPcr) ❌ ❌ ✅² ✅² ✅ ✅*
FMOVEM FP move multiple ❌ ❌ ✅² ✅² ✅ ✅*
FMOVECR (unimplemented in 68040 hardware) FP move constant ROM (68881+ silicon; software-handled on AmigaOS via 68040.library / 68060.library) ❌ ❌ ✅² ✅² ⚠³ ⚠¹
FMUL FP multiply ❌ ❌ ✅² ✅² ✅ ✅
FNEG FP negate ❌ ❌ ✅² ✅² ✅ ✅
FNOP FP no-op ❌ ❌ ✅² ✅² ✅ ✅
FRESTORE Restore FPU state frame (supervisor) ❌ ❌ ✅² ✅² ✅ ✅
FSAVE Save FPU state frame (supervisor) ❌ ❌ ✅² ✅² ✅ ✅
FScc FP set on condition ❌ ❌ ✅² ✅² ✅ ⚠¹
FTRAPcc FP trap on condition ❌ ❌ ✅² ✅² ✅ ⚠¹
FSGLDIV Single-precision FP divide ❌ ❌ ✅² ✅² ✅ ✅
FSGLMUL Single-precision FP multiply ❌ ❌ ✅² ✅² ✅ ✅
FSQRT FP square root ❌ ❌ ✅² ✅² ✅ ✅
FSUB FP subtract ❌ ❌ ✅² ✅² ✅ ✅
FTST FP test ❌ ❌ ✅² ✅² ✅ ✅
#### Monadic transcendentals (68881+ silicon; 68882 silicon identical; software-handled on AmigaOS via 68040.library / 68060.library)
Mnemonic Operation 68000 68010 68020 68030 68040 68060
FACOS FP arccosine ❌ ❌ ✅² ✅² ⚠³ ⚠¹
FASIN FP arcsine ❌ ❌ ✅² ✅² ⚠³ ⚠¹
FATAN FP arctangent ❌ ❌ ✅² ✅² ⚠³ ⚠¹
FATANH FP hyperbolic arctangent ❌ ❌ ✅² ✅² ⚠³ ⚠¹
FCOS FP cosine ❌ ❌ ✅² ✅² ⚠³ ⚠¹
FCOSH FP hyperbolic cosine ❌ ❌ ✅² ✅² ⚠³ ⚠¹
FETOX (unimplemented in 68040 hardware) FP eˣ ❌ ❌ ✅² ✅² ⚠³ ⚠¹
FETOXM1 (unimplemented in 68040 hardware) FP eˣ−1 ❌ ❌ ✅² ✅² ⚠³ ⚠¹
FGETEXP FP get exponent ❌ ❌ ✅² ✅² ⚠³ ⚠¹
FGETMAN FP get mantissa ❌ ❌ ✅² ✅² ⚠³ ⚠¹
FLOG10 FP log₁₀ ❌ ❌ ✅² ✅² ⚠³ ⚠¹
FLOG2 FP log₂ ❌ ❌ ✅² ✅² ⚠³ ⚠¹
FLOGN FP ln ❌ ❌ ✅² ✅² ⚠³ ⚠¹
FLOGNP1 (unimplemented in 68040 hardware) FP ln(x+1) ❌ ❌ ✅² ✅² ⚠³ ⚠¹
FSIN FP sine ❌ ❌ ✅² ✅² ⚠³ ⚠¹
FSINCOS (unimplemented in 68040 hardware) FP sine+cosine ❌ ❌ ✅² ✅² ⚠³ ⚠¹
FSINH FP hyperbolic sine ❌ ❌ ✅² ✅² ⚠³ ⚠¹
FTAN FP tangent ❌ ❌ ✅² ✅² ⚠³ ⚠¹
FTANH FP hyperbolic tangent ❌ ❌ ✅² ✅² ⚠³ ⚠¹
FTENTOX FP 10ˣ ❌ ❌ ✅² ✅² ⚠³ ⚠¹
FTWOTOX FP 2ˣ ❌ ❌ ✅² ✅² ⚠³ ⚠¹

Dyadic transcendentals (68881+ silicon; FMOD/FREM/FSCALE software-handled on AmigaOS via 68040.library / 68060.library)

Mnemonic Operation 68000 68010 68020 68030 68040 68060
FMOD FP modulo ❌ ❌ ✅² ✅² ⚠³ ⚠¹
FREM FP IEEE remainder ❌ ❌ ✅² ✅² ⚠³ ⚠¹
FSCALE FP scale exponent ❌ ❌ ✅² ✅² ⚠³ ⚠¹

¹ 68060 FPU software support on AmigaOS: the 68060 FPU does not implement these in silicon; they trap on vector 11 (unimplemented F-line) and are handled by AmigaOS CPU-support software, typically 68060.library on systems configured for a 68060.

² Requires an external MC68881 or MC68882 floating-point coprocessor on the MC68020/MC68030, connected through the M68000 coprocessor interface. The full MC68040 and MC68060 have an FPU integrated on-die.

³ 68040 FPU software support on AmigaOS: the 68040 FPU does not implement these in silicon; they trap on vector 11 (unimplemented F-line) and are handled by AmigaOS CPU-support software such as 68040.library.

The MC68LC040 and MC68EC040 have no FPU silicon. Legal MC68040/MC68881/MC68882 floating-point instructions are treated as unimplemented floating-point instructions and enter the F-line exception path (vector 11); system software can emulate them. See the processor-specific appendices of MC68040UM for the variant stack-frame details.

* The 68060 retained most forms of FMOVE and FMOVEM but the dynamic-register-list variant of FMOVEM.X and the #immediate, list of 2 or 3 control registers form of FMOVEM.L are unimplemented (emulated). See 68060 specific deltas for the exact restrictions.

68000 specific deltas

The MC68000 (Motorola, 1979) is the baseline for the 680x0 programming model. Later family members preserve most user-level object code but introduce a small number of privilege, instruction, MMU, and implementation differences documented below.

Architecture overview

  • 16-bit external data bus (the 68008 had an 8-bit bus; the 68000 itself had 16 bits)
  • 24-bit external address bus (16 MiB linear address space)
  • 8 data registers (D0-D7, 32-bit) and 8 address registers (A0-A7, 32-bit; A7 is the active stack pointer, with USP and SSP selected by the S bit of the status register)
  • Two privilege levels (user, supervisor) with separate stack pointers
  • Status Register (SR) — 16-bit, low byte is the condition code register (CCR) accessible from user mode
  • Program Counter (PC) — 32-bit register but only low 24 bits externally addressable
  • Two MOS 8520 CIA chips provide timers and peripheral I/O services used by the keyboard, parallel port, floppy-control signals and other system functions. They are CIA-family devices related to the MOS 6526; the Amiga's main serial UART is implemented in Paula, not in the CIAs
  • No on-chip MMU or FPU (both were external or added on later CPUs)
  • No instruction cache (added on the 68020 and later)

Addressing modes supported by the 68000

The 68000 supports 14 addressing modes (the original set; 68020 adds more):

Mode Syntax example Notes
Data register direct Dn
Address register direct An One extra over data regs
Address register indirect (An)
Address register indirect with post-increment (An)+ For byte operands, A7 increments by 2 rather than 1 to preserve word alignment
Address register indirect with pre-decrement -(An) For byte operands, A7 decrements by 2 rather than 1
Address register indirect with 16-bit displacement (d16,An)
Address register indirect with index (8-bit) (d8,An,Xn) Baseline 68000/68010 brief-index form; extended indexing/full-extension forms arrive with 68020
Absolute short (xxx).W 16-bit value sign-extended to the processor address width
Absolute long (xxx).L 32-bit address
Program counter indirect with displacement (d16,PC) For position-independent code
Program counter indirect with index (d8,PC,Xn)
Immediate (data) #<data> Byte, word, or longword
Immediate (address) #<address> Valid as immediate data for instructions such as MOVEA; LEA does not accept an immediate source
Status register / CCR forms SR / CCR Privilege depends on instruction and CPU: MOVE to SR is privileged; MOVE from SR becomes privileged on 68010+; CCR access is non-privileged

Instruction set summary

The MC68000 baseline instruction set includes MOVE to CCR but not MOVE from CCR; the latter was introduced by the MC68010. Because Motorola documentation sometimes presents family-wide summary tables that include instructions from more than one family member, this article avoids assigning a single “mnemonic count” to the MC68000 unless the counting convention is stated explicitly.

The important baseline distinctions used by the matrix are:

  • MOVE to CCR is available on the MC68000.
  • MOVE from CCR, BKPT, MOVEC, MOVES, and RTD are MC68010-and-later additions.
  • MOVE from SR is unprivileged on the MC68000 but privileged on MC68010 and later processors.
  • CAS, CAS2, bit-field instructions, CHK2/CMP2, PACK/UNPK, TRAPcc, long multiply/divide forms, and the generic coprocessor instruction set arrive with the MC68020.

Semantics notes specific to the 68000

  • MOVE from SR is unprivileged on the 68000 (subsequent CPUs make it privileged for Popek-Goldberg virtualization compliance).
  • RTE uses a simple 3-word stack frame (status + PC); later CPUs add expanded formats.
  • No instruction cache — every instruction fetch is a bus cycle (the 68010 introduced a 3-word prefetch queue; the 68020 added a 256-byte instruction cache).
  • Atomic read-modify-write is supported — TAS uses an indivisible read-modify-write bus cycle and is the baseline synchronization primitive on the 68000. Later processors add CAS/CAS2; system-level cache/coherency policy still matters in multiprocessor designs.

Amiga relevance

The 68000 powered the early Amiga line in two package variants:

  • DIP-64 (through-hole): Amiga 1000 (1985), A500 (1987), A2000 (1987).
  • PLCC-68 (surface-mount): CDTV (1991), Amiga 600 (1992).

The A600 used the surface-mount PLCC variant to fit the more compact low-cost case (the lower nominal clock compared to the A500 is not an A600-specific cost-saving measure — it is determined by the video standard: PAL Amiga models (A500, A600, A1200, etc.) run at ≈ 7.09379 MHz while NTSC models (A500, A600, A1200, etc.) run at ≈ 7.15909 MHz, both across all model lines). Later Amiga models (A1200, A3000, A4000) shipped with 68020/030/040-class CPUs. Software specifically targeting the 68000 generally migrates well to later processors, subject to the privilege and compatibility caveats described in this reference; software that uses later-CPU instructions obviously cannot run on a plain 68000.

MC68000-family variants

Motorola/NXP documentation distinguishes the original MC68000 and several related implementations. Speed suffixes such as -8, -10, etc. are speed grades, not separate ISA variants. The commonly documented family members relevant here are:

Variant Data bus Address bus Notes
MC68000 16-bit 24-bit (16 MiB) original implementation
MC68008 8-bit 20-bit or 22-bit, depending on package/version reduced external bus width and pin count
MC68HC000 16-bit 24-bit CMOS implementation of the MC68000
MC68HC001 selectable 8-/16-bit 24-bit CMOS derivative with selectable external data-bus width
MC68EC000 16-bit 24-bit lower-cost embedded implementation
MC68SEC000 16-bit 24-bit static, low-power implementation

These parts retain the MC68000 programming model unless their individual documentation states otherwise; packaging, electrical characteristics and bus-interface details differ between variants.

68010 specific deltas

The 68010 is binary-compatible with 68000 user-mode code except for the important privilege change to MOVE from SR: on the 68010 it becomes supervisor-only. To preserve user-mode access to the condition codes, the 68010 adds MOVE from CCR. MOVE to CCR already exists on the 68000 and remains non-privileged.

The 68010 also introduced an expanded RTE stack frame (the throwaway frame and bus-cycle restart frame) for bus-error recovery and virtual-memory support — the instruction is still called RTE, but its stack frame format differs from the 68000's. OS-level exception handlers must check the format word on the stack to distinguish the two cases.

In addition to MOVE from CCR, the 68010 added four other mnemonics:

Mnemonic Category Purpose
BKPT System control Run breakpoint acknowledge cycle; trap as illegal instruction if no ack
MOVEC Data movement Move to/from control registers (VBR, SFC, DFC, USP on 68010)
MOVES Data movement Move with alternate function code (supervisor)
RTD Program control Return from subroutine and deallocate parameters: pop PC from the stack, then add a sign-extended 16-bit displacement to SP ((SP) -> PC; SP + 4 + d_n -> SP)

A loop mode accelerator was also added. When a suitable single-instruction loop is controlled by DBcc, the processor can execute the loop without repeatedly fetching the loop instruction from the external bus. This is an internal loop/prefetch mechanism, not a general-purpose instruction cache.

MC68010 variants

This reference treats the MC68010 as the architectural 68010 target. Do not infer additional EC, SEC or LC 68010 variants by analogy with later Motorola naming unless a specific Motorola part document is available for that device.

The 68010 was not widely used in Amiga hardware — the A500/A1000/A2000 used the 68000, and Commodore later moved to 68020-class processors in machines such as the A1200/CD32. The Macintosh LC used a 68020-class CPU and the Sun-3/80 used a 68030, not a 68010.

68020 specific deltas

The MC68020 was the first 680x0 family member with a 32-bit data path (previous were 16-bit on the data bus), 32-bit address space (4 GiB linear), an on-chip instruction cache (256 bytes), and dynamic bus sizing (8/16/32-bit port auto-detection). It was also the first to add a bit-field unit and a coprocessor interface.

MC68020 variants

Variant Notes
MC68020 full implementation with a 32-bit external address bus (4 GiB address space) and the M68000 coprocessor interface
MC68EC020 ("Embedded Controller") 24-bit external address bus (16 MiB address space); omits several bus-interface signals present on the MC68020 but retains the M68000 coprocessor interface, including support for Motorola coprocessors such as the MC68881/MC68882

Used in: Commodore CD32 (14.3 MHz) and as the base CPU family of the Amiga 1200, whose 68EC020 is limited to a 24-bit external address bus.

The MC68020/MC68EC020 has no integrated MMU. Memory-management functionality, when required, is external to the CPU; do not describe the MC68EC020 as having a separately fabricated "MMU coprocessor bus" disabled while retaining only an FPU interface. The processor's documented M68000 coprocessor interface is common to MC68020/EC020.

Per MC68020UM Table 1-2 (pp. 1-10 → 1-11), the 68020 added the following instructions not present on the 68000/68010:

Bit-field instructions (8)

BFCHG, BFCLR, BFEXTS, BFEXTU, BFFFO, BFINS, BFSET, BFTST

Atomic memory operations (2)

CAS, CAS2 (dual-operand)

Range-check instructions (2)

CHK2, CMP2

BCD packing (2)

PACK, UNPK

Conditional trap (1)

TRAPcc (with .W and .L operand-size variants)

Module call/return (2) — 68020 only

CALLM, RTM

Coprocessor interface (7)

cpBcc, cpDBcc, cpGEN, cpRESTORE, cpSAVE, cpScc, cpTRAPcc — define the generic M68000-family coprocessor instruction protocol introduced with the MC68020. Later processors retain relevant coprocessor instruction encodings, but their integrated FPU/MMU implementations must be described according to the processor-specific manuals rather than assuming the MC68020 external-coprocessor hardware interface.

Long multiply/divide variants

MULS.L (wide, Dh:Dl) 32×32→64, MULU.L (wide, Dh:Dl) 32×32→64, DIVS.L (<ea>,Dr:Dq) 64÷32→32r:32q, DIVU.L (<ea>,Dr:Dq) 64÷32→32r:32q, DIVSL.L (<ea>,Dr:Dq) 32÷32→32r:32q, DIVUL.L (<ea>,Dr:Dq) 32÷32→32r:32q.

Other extensions

  • EXTB.L — sign-extend byte→longword (the 68000/68010 had EXT.W and EXT.L for byte→word→longword only; 68020 adds byte→long).

Addressing modes introduced on 68020

The 68020 added several addressing modes not available on earlier CPUs:

  • Address register indirect with index (8-bit and 32-bit displacements)
  • Memory indirect ((d16,An) and (d32,An,Xi) post-indexed variants)
  • PC-relative with index (8-bit and 32-bit displacements, scaled index)
  • Scaled index (An,Xi*scale where scale ∈ {1, 2, 4, 8})

The full M68000 base addressing modes (data/address register direct, address register indirect, immediate, absolute) remain valid.

Virtual-machine support

The MC68020 retains and extends the restartable-exception and privilege mechanisms introduced with the MC68010, making it suitable for virtual-memory and virtual-machine operating-system designs. Avoid treating the MC68020 as a clean 'partial → complete Popek-Goldberg' boundary: the key 68000 virtualization problem (MOVE from SR in user mode) was already changed on the MC68010.

68030 specific deltas

The MC68030 is the 68020 with an integrated MMU (the first M68k CPU with on-die MMU) and two on-chip caches (256 bytes each, separate instruction and data caches with burst-mode fills). It is largely binary-compatible with the 68020 — almost every 68020 instruction works on the 68030 — with two notable exceptions: CALLM and RTM (the 68020's module-management instructions) were dropped on the 68030 per MC68030UM Table 1-2 (they appear in MC68020UM Table 1-2 but not in the 68030 instruction set). It adds a new family of MMU-control instructions.

MC68030 variants

Variant MMU Notes
MC68030 ✅ on-die PMMU (full part) burst-mode bus, separate I/D caches
MC68EC030 ("Embedded Controller") ❌ no on-die MMU embedded variant without the integrated MC68030 MMU

The pattern is the same as 68040/68060: "EC" suffix = MMU disabled. The 68030 does not have an LC variant corresponding to "FPU disabled" because the FPU on this generation is the external 68881/68882 coprocessor (the 68030 itself has no integrated FPU to disable).

Per MC68030UM Table 1-2 (pp. 1-12 → 1-13), the 68030 instruction set is the 68020 set plus the following MMU instructions (and drops CALLM and RTM):

MMU instructions added on 68030 (8)

Mnemonic Purpose
PFLUSH Flush ATC entries (entry pointed to by An or all entries)
PFLUSHA Flush all entries in the ATC
PLOADR / PLOADW Load an entry into the ATC (read or write access mode)
PMOVE Move to/from MMU registers: CRP, SRP, TC, TT0, TT1, MMUSR
PMOVEFD Move to/from selected MMU registers while suppressing the normal ATC flush side effect
PTESTR / PTESTW Probe a logical address for translation (read or write access mode)

These instructions communicate with the on-die MMU to manage the Address Translation Cache (ATC) — the 22-entry fully-associative cache that holds recent virtual-to-physical address translations. The PMOVE family accesses the MMU control registers (CRP, SRP, TC, TT0, TT1, MMUSR) which define the translation table structure.

Instructions dropped or replaced on 68030

The 68030 keeps everything else from the 68020 — CALLM, RTM are listed in the 68020UM Table 1-2 but not in the 68030UM Table 1-2, meaning Motorola dropped them with the 68030 (CALLM/RTM were 68020-specific module-management instructions that never saw widespread use outside of a few niche systems). Bit-field, atomic, range, BCD, conditional-trap, and long-MUL/DIV are all retained unchanged.

Addressing modes on 68030

The 68030 retains the MC68020 addressing-mode set (per MC68030UM §1.4, Table 1-1) — no new addressing modes are introduced. The 68030's additions are MMU instructions (PFLUSH, PLOAD, PMOVE, PTEST, etc.).

Cache and bus improvements

  • 256-byte instruction cache + 256-byte data cache on-chip (separate, with burst-mode fills). New MMU signal CIIN (cache inhibit input) lets external hardware mark bus regions as non-cacheable.
  • Burst-mode bus — fills 4 long words (16 bytes) per cache-line fill in a single burst, halving effective memory latency.
  • Dynamic bus sizing extended — full 8/16/32-bit port auto-detection on both code and data fetches.

MMU on the 68030

The 68030's MMU is a paged memory-management unit (PMMU) with these features:

  • 32-bit logical → 32-bit physical translation
  • 22-entry fully-associative ATC
  • 8 page sizes from 256 B to 32 KB
  • 2 transparent translation regions (always pass-through)
  • CPU/supervisor root pointer registers (CRP / SRP)
  • Write protection and supervisor protection attributes
  • 3-bit function codes (FC0-FC2) for separate address spaces

The 68030 MMU instruction set is built around PMOVE + PFLUSH + PLOAD + PTEST. The 68040 changes the MMU programming model to MOVEC-based control-register access plus its own PFLUSH/PTEST forms. The full MC68060/MC68LC060 retain native PFLUSH-family operations and add PLPA; PTEST is unimplemented on the 68060. On the MC68EC060, which has no MMU, MMU-specific operations have variant-specific no-effect/illegal behavior as documented by MC68060UM.

68040 specific deltas

The MC68040 is the first Amiga-class CPU with integrated MMU and FPU on-die.

MC68040 variants

Per MC68040UM (preface, "Documentation package for the MC68040, MC68040V, MC68LC040, MC68EC040, and MC68EC040V"), the 68040 family has five documented variants:

Variant MMU FPU Notes
MC68040 ✅ on-die ✅ on-die full part (5V)
MC68040V ✅ on-die ❌ (no FPU) 3.3V static; same IU+MMU as MC68040 but no FPU (raises unimplemented FPU exception); adds SCD/LFO/LOC pins and low-power stop mode; not pin-compatible with MC68040
MC68LC040 ("Low Cost") ✅ on-die ❌ (no FPU) pin-compatible with MC68040; no FPU silicon per MC68040UM §1.1.1 — legal FPU instructions enter the documented unimplemented floating-point exception path, allowing system software to provide emulation
MC68EC040 ("Embedded Controller") ❌ no on-die MMU ❌ (no FPU) embedded variant without the integrated MMU or FPU
MC68EC040V ❌ ❌ voltage variant of EC040 (3.3V)

Pattern (carried forward conceptually to 68060): LC variants retain the MMU but omit the FPU; EC variants omit both integrated MMU and FPU. On the 68040-family no-FPU variants, legal floating-point instructions generate the documented unimplemented floating-point/F-line exception so that system software can emulate them.

The instruction matrix above assumes the full MC68040 part. On the MC68040V, MC68LC040, and MC68EC040/MC68EC040V, FPU instructions are not executed by hardware and enter the unimplemented floating-point/F-line exception path (vector 11); an operating system may provide software emulation. On EC variants the integrated MMU is absent, so the full-part MMU column does not apply.

68040 mask sets (per community verification)

Per the community-maintained list (compiled from multiple sources including the original Amiga past), the following 68040 mask revisions are documented:

Mask Revision MMU FPU Geometry [µm] max observed speed [MHz] Remark
E71M — ✅ — 0.65 40 (none yet)
E23G — ✅ — 0.65 40 (none yet)
D39H — ✅ — 0.8 40 fan should be set to "cool", not "quiet"
D43B — ✅ — 0.8 25 May run at 33MHz with over/under-volting
D50D — ✅ — 0.8 33 runs very hot, don't run w/o cooler
D98D — ✅ — 0.8 33 XC-mask, possibly faster
E31F — ✅ — 0.65 40 (none yet)
E26A — TBD TBD 0.65 TBD (likely 40) Not tested - no sample available
E42K — ✅ — 0.65 40 Full MC qualification
K63H — ✅ — 0.57 40 fastest 5V-type, so far untested
L88M — ✅ — 0.57 40 fastest 5V-type, so far untested
F54F — ✅ — 0.5 40 3.3V type, not supported by ACA1240/1260
D33T — ✅ — 0.5 40 3.3V type, not supported by ACA1240/1260

Bit-field instructions (carried over from 68020)

The 68020 introduced dynamic bit-field access. All eight bit-field mnemonics — BFCHG, BFCLR, BFEXTS, BFEXTU, BFFFO, BFINS, BFSET, BFTST — are carried over on the 68040.

Atomic compare-and-swap

CAS and CAS2 were introduced on the 68020. The 68040 retains both CAS and CAS2; on the 68060, CAS2 (the dual-operand form) is unimplemented in hardware and is handled through the vector-61 compatibility path by 68060.library on AmigaOS.

Multi-precision multiply and divide

The 68020 introduced the long forms of multiply and divide:

Mnemonic Operation
MULS.L 32×32→32
MULS.L (wide, Dh:Dl) 32×32→64
MULU.L 32×32→32
MULU.L (wide) 32×32→64
DIVS.L 32÷32→32q
DIVU.L 32÷32→32q
DIVSL.L 32÷32→32r:32q
DIVUL.L 32÷32→32r:32q

The 68040 carries all of these.

68040-specific cache, MMU, and block-move instructions

The 68040 adds new cache/block-move instructions and revises the MMU instruction forms. PFLUSH and PTEST are not new mnemonic names—they already exist on the MC68030—but their encodings/semantics belong to the 68040 MMU programming model:

Mnemonic Category Purpose
CINV (CINVL/CINVP/CINVA) Cache control Invalidate instruction/data cache lines (68040+)
CPUSH (CPUSHL/CPUSHP/CPUSHA) Cache control Push dirty data cache lines and invalidate (68040+)
MOVE16 Data movement 16-byte aligned block move; register-postincrement and absolute-long forms are defined
PFLUSH (PFLUSH/PFLUSHN/PFLUSHA/PFLUSHAN) MMU control Flush ATC entries — replaces 68030's PMOVE interface
PTEST (PTESTR/PTESTW) MMU control Probe ATC entry status — replaces 68030's PMOVE interface

Dropped/replaced instructions

The 68040 drops or replaces several instructions from the 68030:

  • MMU interface replaced: The 68030's PMOVE (move to/from MMU registers: CRP, SRP, TC, TT0, TT1, MMUSR) is replaced on the 68040 by MOVEC and the PFLUSH/PTEST instructions. Code that talks to the 68030 MMU must be rewritten for the 68040.
  • Move-from-SR still privileged (carried over from 68010+).

FPU on the 68040

The 68040 has an integrated FPU (no external 68882 needed). It implements a substantial, commonly used subset of the MC68881/MC68882 floating-point ISA in hardware, while software completes compatibility for the remaining operations and data types:

  • The monadic transcendentals, FINT, FINTRZ, FGETEXP, FGETMAN, FMOD, FREM, FSCALE, FMOVECR, and related compatibility functions are not executed directly in 68040 silicon; on AmigaOS they are handled by CPU-support software such as 68040.library. By contrast, conditional floating-point instructions such as FDBcc, FScc, and FTRAPcc are implemented by the MC68040 itself. Unimplemented floating-point instructions use vector 11.
  • FRESTORE and FSAVE frame formats differ slightly between the 68882 and the integrated 68040 FPU; OS code must dispatch correctly.

68060 specific deltas

The MC68060 is the final M68k family processor designed for high-performance desktop computing. It was architected for superscalar dual-issue execution: two integer instructions can dispatch and complete in parallel. To meet timing closure at the target clock rate, the 68060 leaves several earlier instructions or forms unimplemented in hardware. On AmigaOS, the resulting compatibility exceptions are normally handled by CPU-support software supplied for the accelerator/system, commonly exposed as 68060.library.

Unimplemented integer instructions (68060.library on AmigaOS)

Per MC68060UM Appendix C.2, the following 68020/68030/68040 instructions are unimplemented in 68060 hardware:

Mnemonic Operation Emulated form
DIVU.L <ea>,Dr:Dq Unsigned divide 64÷32→32r,32q wide-input form (64-bit dividend)
DIVS.L <ea>,Dr:Dq Signed divide 64÷32→32r,32q wide-input form (64-bit dividend)
MULU.L <ea>,Dr:Dq Unsigned multiply 32×32→64 wide-output form (64-bit result)
MULS.L <ea>,Dr:Dq Signed multiply 32×32→64 wide-output form (64-bit result)
MOVEP Dx,(d16,Ay) Move peripheral data → memory both directions
MOVEP (d16,Ay),Dx Move peripheral data → register both directions
CHK2 <ea>,Rn Check register against bounds any size
CMP2 <ea>,Rn Compare against bounds any size
CAS2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2) Compare-and-swap dual any size
CAS Dc,Du,<ea> (misaligned) Compare-and-swap with misaligned ea alignment condition

These all raise exception vector 61 (unimplemented integer instruction). The exception handler reads the stacked PC, decodes the instruction, emulates it using implemented instructions, and resumes via RTE.

Rule: on the MC68060, the 64-bit-result multiply forms (MULS.L/MULU.L using a register pair) and the 64-bit-dividend forms of DIVS.L/DIVU.L are unimplemented and require the vector-61 software path. The ordinary 32-bit-result multiply/divide forms are implemented in hardware, and DIVSL.L/DIVUL.L (32÷32 with quotient and remainder in Dr:Dq) are also hardware-implemented.

MOVEP is software-handleable on the 68060: the CPU raises exception vector 61, and on AmigaOS the installed 68060 CPU-support software (typically 68060.library) can emulate the instruction. It is therefore not equivalent to an opcode that is simply absent with no compatibility path.

Unimplemented floating-point instructions (68060.library on AmigaOS)

Per MC68060UM Section 6.5.1 (Table 6-11), the 68060 does not implement the following 68881/68882/68040 FPU instructions — they raise vector 11 (unimplemented F-line):

Category Mnemonics
Monadic transcendentals FACOS, FASIN, FATAN, FATANH, FCOS, FCOSH, FETOX, FETOXM1, FGETEXP, FGETMAN, FLOG10, FLOG2, FLOGN, FLOGNP1, FSIN, FSINCOS, FSINH, FTAN, FTANH, FTENTOX, FTWOTOX
Dyadic / related arithmetic FMOD, FREM, FSCALE
Miscellaneous FMOVECR, FTRAPcc, FDBcc, FScc

The following effective-address forms are a separate class: FMOVEM.X with a dynamic register list, FMOVEM.L immediate masks selecting multiple control registers, and immediate extended/packed source forms. These generate the unimplemented effective-address exception (vector 60) rather than the floating-point-unimplemented-instruction path on vector 11.

The FPU is still integrated on-die on the 68060, and the following remain hardware-implemented: FABS, FADD, FBcc, FCMP, FDIV, FINT, FINTRZ, FMOVE (most forms), FMOVEM (most forms), FMUL, FNEG, FNOP, FRESTORE, FSAVE, FSGLDIV, FSGLMUL, FSQRT, FSUB, FTST. FSCALE is not in this native list; it is one of the unimplemented floating-point operations.

FINT and FINTRZ are documented for both the MC68881 and MC68882 and are implemented in MC68060 hardware. On the MC68040 they are part of the compatible floating-point ISA but are not implemented by the on-chip FPU; AmigaOS CPU-support software such as 68040.library supplies them through the unimplemented floating-point exception path.

MMU and cache on the 68060

The 68060 family has three variants that differ in MMU and FPU presence:

Variant MMU FPU Notes
MC68060 ✅ on-die ✅ on-die full part
MC68LC060 ("Low Cost") ✅ on-die ❌ (no FPU) legal FP instructions require the floating-point exception/software-support path
MC68EC060 ("Embedded Controller") ❌ no on-die MMU ❌ (no FPU) embedded variant without the integrated MMU or FPU

The MC68060 and MC68LC060 both have an on-die MMU configured through the 68040/68060-style control registers. The MC68EC060 omits the integrated MMU; software must treat it as a non-MMU variant rather than assuming a standard external PMMU interface.

68060 mask sets (per community verification)

Per the community-maintained list (compiled from multiple sources including the original Amiga past), the following 68060 mask revisions are documented:

Mask Revision MMU FPU Geometry [µm] max observed speed [MHz] Remark
D11W 1 ✅ — 0.5 50 rare prototype
F43G 1 ✅ — 0.5 66 Often found in 68EC060-marked chips
F84W -- -- -- 0.0 0 Fake chip sold as Rev.6
F10H -- -- -- 0.0 0 Fake chip sold as Rev.6
G65V 5 ✅ — 0.5 75 Often found in 68EC060-marked chips
G59Y 4 ✅ — 0.42 100 Full MC qualification
E41J 6 ✅ — 0.42 100 Full MC qualification

The full MC68060/MC68LC060 implement the PFLUSH family (PFLUSH, PFLUSHN, PFLUSHA, PFLUSHAN) for their on-die ATCs. PTEST is unimplemented on the 68060; PLPA (load physical address) provides a diagnostic/table-walk-oriented alternative. The MC68EC060 has no MMU, so MMU-specific opmodes have variant-specific behavior and must not be described as the behavior of the full MC68060.

The MC68060 family retains separate on-chip instruction and data caches (8 KiB each on the full MC68060 design); cache-control behavior should be checked against the exact LC/EC variant documentation when writing low-level system code.

The 68060 retains the 68040's CINV and CPUSH cache-control instructions for managing its on-die 8 KB instruction cache + 8 KB data cache (the 68060 uses the superscalar pOEP/sOEP execution pipelines).

Superscalar execution model

The 68060 is the only classic 680x0 with superscalar dual-issue execution. Its integer execution core contains a primary Operand Execution Pipeline (pOEP) and a secondary Operand Execution Pipeline (sOEP). Instruction pairing depends on the superscalar classification in MC68060UM Section 10, operand dependencies, and addressing-mode restrictions:

  • pOEP-only: instructions that require the primary pipeline or otherwise block pairing
  • pOEP / sOEP eligible: simple integer operations and moves that meet the manual's pairing rules
  • pOEP while allowing sOEP activity: selected branches/FPU cases and other classes explicitly identified by the timing tables
  • Pairing barriers / multi-cycle classes: operations identified by the manual as locking or occupying resources needed by the secondary pipeline. Do not infer a barrier solely from whether an instruction changes the CCR; use the pOEP/sOEP classification and dependency rules.

Compiled code that respects these barriers can see ~1.5–1.8× the throughput per clock vs. 68040. The AmigaOS developer community (PhxASS vbcc) had specific scheduling pragmas to emit dual-issue-friendly instruction pairs.

AmigaOS 68060 CPU-support library

For this Amiga-oriented reference, the relevant compatibility layer is the AmigaOS CPU-support library rather than Motorola/Freescale's standalone software packages. On a 68060-equipped Amiga, 68060.library is the conventional system component used by the accelerator/OS support stack to install the required CPU exception handlers and provide compatibility for instructions and floating-point operations that are not implemented directly in MC68060 hardware.

The hardware exception behavior remains architectural: unimplemented integer cases use vector 61, unimplemented effective-address forms use vector 60, and unimplemented F-line/floating-point cases use vector 11. 68060.library provides the AmigaOS-side handling expected by this wiki's target environment. Exact implementation details can still vary between accelerator vendors and library revisions.

CAS2 and CAS semantics on 68060

  • CAS2 (68020/030/040): unimplemented in 68060 hardware — handled through the vector-61 compatibility path by 68060.library on AmigaOS
  • CAS (aligned): implemented in hardware
  • CAS with a misaligned effective address: unimplemented in MC68060 hardware and handled through the vector-61 software-support path if an emulator is installed

Software should not rely on deliberately misaligned CAS as a portable synchronization technique: the MC68060 treats that form as an unimplemented integer case.

Compatibility matrix summary

The family is broadly upward object-code compatible, but not strictly monotonic: several instructions or instruction forms disappear from hardware on later processors, and some are recovered through exception-driven software support.

To keep the count internally reproducible, the table below counts instruction groups exactly as represented by rows in the master matrix above. A combined row such as ASL / ASR counts as one matrix group, while separately listed forms such as narrow/wide multiply forms count separately. For MC68020/MC68030, a ✅ floating-point row means hardware support through the configured external MC68881/MC68882 coprocessor. These are therefore article matrix counts, not an official Motorola count of unique mnemonic spellings or opcode encodings.

Metric 68000 68010 68020 68030 68040 68060
Matrix instruction groups supported 80 85 158 162 162 162
Hardware-supported in the reference configuration 80 85 158 162 135 128
Software-handled / emulated groups 0 0 0 0 27 34
Unsupported groups represented in the matrix 88 83 10 6 6 6

For the MC68060, the 34 software-handled matrix groups comprise 6 integer groups (CMP2, CHK2, CAS2, MOVEP, wide MULS.L, wide MULU.L), 21 monadic floating-point operations, 3 dyadic/related floating-point operations (FMOD, FREM, FSCALE), and 4 miscellaneous floating-point operations (FDBcc, FScc, FTRAPcc, FMOVECR). Additional individual encodings/forms such as wide DIVS.L/DIVU.L, misaligned CAS, and restricted floating-point effective-address forms also trap for software handling but share a matrix row with a hardware-supported form.

Transition Important compatibility points
68000 → 68010 MOVE from SR becomes privileged; MOVE from CCR, BKPT, MOVEC, MOVES, and RTD are added.
68010 → 68020 32-bit addressing/bus model, scaled and memory-indirect addressing, bit fields, CAS/CAS2, CHK2/CMP2, PACK/UNPK, TRAPcc, long multiply/divide, and coprocessor instructions are added.
68020 → 68030 CALLM/RTM are removed; integrated MMU instructions are added; the rest of the mainstream 68020 integer ISA is retained.
68030 → 68040 MMU programming model changes; CINV, CPUSH, and MOVE16 are added; a hardware FPU implements a common 68881/68882 subset while 68040.library supplies the AmigaOS compatibility path for the remainder.
68040 → 68060 Superscalar pOEP/sOEP execution; several integer forms (MOVEP, CAS2, CHK2, CMP2, wide MUL/DIV, misaligned CAS) and many floating-point operations trap for software handling; PTEST is unimplemented and PLPA is added.

For the MC68060, the key exception paths are vector 61 for unimplemented integer instructions, vector 60 for unimplemented effective-address forms, and vector 11 for unimplemented/disabled F-line floating-point cases.

Exception vector table (base + key per-CPU differences)

The M68k vector table contains 256 long-word entries. On the MC68000 it begins at physical address $000000; on processors with a Vector Base Register (MC68010+) the table can be relocated.

Base MC68000 vector assignments

Vector # Offset Assignment
0 $000 Reset initial SSP
1 $004 Reset initial PC
2 $008 Bus error
3 $00C Address error
4 $010 Illegal instruction
5 $014 Integer divide by zero
6 $018 CHK instruction
7 $01C TRAPV instruction
8 $020 Privilege violation
9 $024 Trace
10 $028 Line 1010 emulator (A-line)
11 $02C Line 1111 emulator (F-line)
12-13 $030-$034 Reserved on MC68000
14 $038 Reserved on MC68000; used as format error on later CPUs
15 $03C Uninitialized interrupt vector
16-23 $040-$05C Reserved
24 $060 Spurious interrupt
25-31 $064-$07C Level 1-7 interrupt autovectors
32-47 $080-$0BC TRAP #0 ... TRAP #15
48-63 $0C0-$0FC Reserved on the base MC68000
64-255 $100-$3FC User-defined vectors

MC68010 and later

The MC68010 adds the VBR and restartable exception-frame machinery. In particular, vector 14 is the format-error vector used when RTE encounters an invalid frame format. Later processors reuse additional previously reserved vectors for FPU/MMU-specific exceptions.

MC68040 floating-point vectors

The MC68040 uses vector 11 for a floating-point unimplemented instruction (also the generic F-line vector). Floating-point arithmetic exceptions occupy vectors 48-55; vector 55 is the floating-point unimplemented-data-type exception. The MC68LC040/MC68EC040 no-FPU variants also route legal floating-point instructions through the F-line/unimplemented path so that software may emulate them.

MC68060 unimplemented-instruction vectors

The MC68060 assignments relevant to software compatibility are:

Vector # Assignment
10 Unimplemented A-line / line-1010 emulator
11 Unimplemented F-line, floating-point disabled, or floating-point unimplemented instruction
55 Floating-point unsupported data type
60 Unimplemented effective address
61 Unimplemented integer instruction
62-63 Reserved / unassigned

Thus M68060 software support uses vector 61 for integer emulation and vector 11 for floating-point/F-line emulation; vector 60 handles the special unimplemented effective-address forms.

Amiga interrupt mapping

On classic Amiga hardware, CPU vectors 25-31 are simply the standard M68k level 1-7 autovectors. The Amiga custom-chip interrupt controller multiplexes system interrupt sources onto levels 1-6; CIA-A contributes through the level-2 PORTS source and CIA-B through the level-6 EXTER source. Level 7 is the non-maskable interrupt level and is not a dedicated “CIA vector.” Expansion hardware should use the operating-system interrupt mechanisms rather than assuming fixed vector ranges such as 64-95 for Zorro devices.

Clock cycle counts

Cycle counts per instruction vary by addressing mode (effective-address calculation adds cycles) and by operand type (register vs memory). The tables below show the best-case base cycle count (typically register-to-register or the fastest addressing mode) for each instruction per CPU. For the full per-mode tables see the corresponding Motorola User's Manual:

  • 68000/68010 — MC68000UM Table 8-1 → 8-9
  • 68020 — MC68020UM Appendix A (per-mode cycle tables)
  • 68030 — MC68030UM Section 9 (per-mode cycle tables)
  • 68040 — MC68040UM Section 10 (per-mode cycle tables)
  • 68060 — MC68060UM Section 10 (Tables 10-6 → 10-25)

68000/68010 base cycle counts (per MC68000UM Table 8-1 → 8-9)

The table is primarily the MC68000 baseline. The MC68010 changes timing for some instructions and adds new instructions, so exact 68010 timing should be taken from the MC68010-specific documentation when cycle accuracy matters.

Mnemonic Best case (regs) Long variant Notes
ABCD 8 Dx,Dy form
ADD 4 8 (long) Dx,Dy form
ADDA 8 An + Dx
ADDI 8 16 #imm, Dx
ADDQ 4 8 #imm, Dx
ADDX 4 8 Dx,Dy form
AND 4 8 Dx,Dy form
ANDI 8 16 #imm, Dx
ASL ASR 6+2n up to 14 register shift by register
Bcc 10 (taken) / 8 (not taken)
BCHG BCLR BSET BTST (reg) 8-12 Dx form
BRA 10
BSR 18
BTST (imm) 8-12
CHK 10+ (trap if fail)
CLR 4-6 6-8 Dx form
CMP 4 6 Dx,Dy form
CMPA 6
CMPI 8 12 #imm, Dx
CMPM 12 20 (Ay)+, (Ax)+
DBcc 10-16 (taken/not-taken)
DIVS.W / DIVU.W 122 / 108 base clocks + EA time word divide only on 68000/68010; data-dependent timing
EOR 4 8 Dx,Dy form
EORI 8 16 #imm, Dx
EXG 6
EXT.W 4
EXT.L 4
ILLEGAL 34
JMP 8 (An) form
JSR 16 (An) form
LEA 4 (An) form
LINK 16
LSL LSR 6+2n up to 14
MOVE 4 4 Dx,Dy (reg-to-reg)
MOVE 8 (byte/word) / 12 (long) (An)+ to (An)+
MOVE to/from SR/CCR/USP 8-12 privilege depends on the specific instruction and CPU; CCR access is not generically supervisor-only
MOVEA 4 4
MOVEM 12+4n (n regs) up to 36 reg-to-mem
MOVEP 16 24 (d16,Ay), Dx
MOVEQ 4
MULS.W / MULU.W 42 / 40 base clocks + EA time word multiply only on 68000/68010; timing is data-dependent
NBCD 8 Dx form
NEG 4 6 Dx form
NEGX 4 6 Dx form
NOP 4
NOT 4 6 Dx form
OR 4 8
ORI 8 16
PEA 12 (An) form
RESET 132
ROL ROR ROXL ROXR 6+2n up to 14
RTD 16 68010+
RTE 20
RTR 20
RTS 16
SBCD 8
Scc 4-8 8-10
STOP 4
SUB 4 8
SUBA 8
SUBI 8 16
SUBQ 4 8
SUBX 4 8
SWAP 4
TAS 4 (reg) / 10 (mem)
TRAP 34
TRAPV 34
TST 4 4
UNLK 12

68020 base cycle counts (per MC68020UM Appendix A)

Mnemonic Best case (regs) Notes
ABCD SBCD NBCD 6 Dx,Dy form
ADD SUB 4 Dx,Dy form
ADDQ SUBQ 4 #imm, Dx
ADDX SUBX 4 Dx,Dy form
ADDI SUBI ANDI ORI EORI CMPI 8 #imm, Dx
AND OR EOR CLR NEG NOT TST NEGX 4 Dx,Dy form
ADDA SUBA CMPA 8
CMP 4 Dx,Dy form
MULS.W MULU.W MULS.L MULU.L 28 (word) / 44 (long) best case, no early-out
DIVS.W DIVU.W 44 word divide, worst case
DIVS.L DIVU.L 92 (best) / 158 (worst) long divide
DIVSL.L DIVUL.L 96-168 assembler long-divide form with quotient/remainder register pair; exact encoding/timing depends on dividend form
EXG 6
EXT.W EXT.L EXTB.L 4
SWAP 4
ASL ASR LSL LSR ROL ROR ROXL ROXR 6+2n up to 14 (per count)
Bcc 10 (taken) / 8 (not) branch timing depends on direction/condition and pipeline state
BRA 10
BSR 18
BCHG BCLR BSET BTST (reg) 8-12
BFCHG BFCLR BFSET BFTST 12-18 68020+
BFEXTS BFEXTU BFINS BFFFO 12-18 68020+
CHK CHK2 CMP2 8+ cycles (trap) 68020+ CHK2/CMP2
CAS CAS2 12+ 68020+
CLR 4 reg
DIVS DIVU 44 (word) / 92-158 (long) variable
EXT 4
ILLEGAL 20
JMP (An) 8
JSR (An) 16
LEA (An) 4
LINK 16
MOVE 4 Dx,Dy (reg-to-reg)
MOVE (long) 8 memory-to-memory
MOVEC 12 supervisor, 68010+
MOVEM 12+4n (n regs) up to 36+
MOVEP 16 (word) / 24 (long) retained from earlier M68k generations; exact timing is CPU-specific
MOVEQ 4
MULS MULU 28-44
NBCD 8
NEG NEGX NOT TST 4
NOP 4
OR EOR AND 4
ORI ANDI EORI 8 (word) / 16 (long)
PACK UNPK 8 68020+
PEA 12
RESET 132
ROL ROR ROXL ROXR 6+2n
RTD 16 68010+
RTE 20
RTR 20
RTS 16
Scc 4-8
STOP 4
SUB 4
SWAP 4
TAS 4 (reg) / 14 (mem)
TRAP 34
TRAPcc 18+ 68020+
TRAPV 34
TST 4
UNLK 12

68030 base cycle counts (per MC68030UM Section 9)

The 68030 generally matches the 68020 cycles for register operands, but the integrated caches significantly reduce effective cycle counts for memory accesses (cache hit: 0 extra cycles; cache miss: penalty added per MC68030UM §9).

Mnemonic Best case (regs) Notes
All register-register ALU ops same as 68020 cache-enabled
MOVE (memory, cache hit) 4 no wait states
MOVE (memory, cache miss) 8+ (bus penalty) depends on memory speed
MOVEM faster than 68020 burst-mode cache fills
PMOVE PFLUSH PTEST PLOAD 12-30 cycles 68030-specific
MULS.L MULU.L 28-44 cycles same as 68020

68040 base cycle counts (per MC68040UM Section 10)

The 68040 uses a six-stage integer pipeline: instruction fetch, decode, effective-address calculate, effective-address fetch, execute, and write-back. It also has separate instruction and data caches, branch-acceleration mechanisms, and an integrated FPU on the full MC68040. Timing format is L + X where L = lead time (cycles the instruction can stall) and X = base execution cycles. The table below gives the best-case base cycle count (typically register-to-register, Dn operand) for each instruction, which is also what the integer unit can sustain in the pipeline at 1 IPC. Effective address calculation cycles (0–3 per Table 10-2) must be added for non-register operands.

Integer arithmetic

Mnemonic Best case (regs) Notes
ADD SUB AND OR EOR TST (D→D) 1 register-to-register
ADD SUB (D→M) 1 memory destination
ADDA SUBA (D→A) 2 (M68040UM Table 10-6)
ADDI SUBI ANDI ORI EORI (reg) 1
ADDQ SUBQ (reg) 1
ADDX SUBX (D→D) 1
ADDX SUBX (M→M) 3 (predecrement); 4 (regular)
CLR (D→D) 1
CLR (D→M) 1 memory destination
CMP (D→D) 1
CMPA (D→A) 2
CMPI (reg) 1
CMPM 1 postincrement
NEG NOT NEGX (D→D) 1
TST (D→D) 1
EXT.W EXT.L EXTB.L 1
SWAP 1
MULS.W MULU.W 2 word multiply
MULS.L MULU.L (32×32→32) 3 long multiply
MULS.L wide MULU.L wide (32×32→64) 4
DIVS.W DIVU.W ≤18 (variable) word divide, conditional
DIVS.L DIVU.L (32÷32→32q) ≤44 (variable) long divide
DIVS.L wide DIVU.L wide (64÷32→32r:32q) 8-44 (worst)
DIVSL.L DIVUL.L (32÷32→32r:32q) 4-44 (worst)
BCD ops (ABCD, SBCD, NBCD) (D→D) 3
BCD ops (M→M) 3 (or 3L+1 for some forms)
NEGX.S NEGX.B 1
MOVE (D→D) 1
MOVE (D→M, byte/word) 1 memory destination
MOVE (D→M, long) 1
MOVEA (D→A) 1
MOVEQ 1
EXG 1 register-register

Logical

Mnemonic Best case (regs) Notes
AND OR EOR (D→D) 1
ANDI ORI EORI (D→D) 1
NOT (D→D) 1
EXG 1

Bit manipulation

Mnemonic Best case (regs) Notes
BCHG BCLR BSET (D→D) 1
BCHG BCLR BSET (M→M) 1 (write-back) atomic for BSET/BCLR
BTST (D→D) 1
BTST (M) 1 (no write-back)

Bit-field (68020+)

Mnemonic Best case (regs) Notes
BFCHG BFCLR BFSET BFTST (reg) 1-2 68040 pipelines BF well
BFEXTS BFEXTU BFINS BFFFO 1-2
PACK UNPK (D→D) 1

Shifts/rotates

Mnemonic Best case (regs) Notes
ASL ASR LSL LSR (D→D, by register) 1 + 1/cycle shift up to 5 for byte, 17 for long
ASL ASR LSL LSR (D→D, immediate) 1 (word) / 1 (long, ≤8) / 2 (long, >8)
ROL ROR ROXL ROXR (D→D, by register) 1 + 1/cycle up to 5 (byte) / 17 (long)
ROL ROR ROXL ROXR (D→D, immediate) 1-2

Program control

Mnemonic Best case Notes
Bcc (predicted correctly) 1 branch cache hit
Bcc (predicted, not taken) 1 dual-issue with next
Bcc (predicted, taken) 1
Bcc (not predicted) 3-5 branch cache miss
BRA (taken) 4
BSR 7
DBcc (count ≥ 0) 4
DBcc (taken) 7
JMP (An) 4
JMP (d16,An) 4
JMP (d8,An,Xn) 6
JSR (An) 5
JSR (d16,An) 5
JSR (d8,An,Xn) 7
LEA (An) 1 fastest of all
LEA (d16,An) 1
LEA (d8,An,Xn) 3
RTS 5
RTR 7
RTE (Format $0) 13 68020+ throwaway
RTE (Format $1) 23 bus cycle restart
RTE (Format $2) 14
RTE (Format $3) 20
RTD 6 68010+
JMP (d16,PC) 5
JSR (d16,PC) 6
NOP 1 one cycle (TRAPF equivalent)
TRAP #n 16 trap + vector fetch
TRAPcc (taken) 19
TRAPcc (not taken) 5
TRAPV (taken) 19
TRAPV (not taken) 5
LINK 5
UNLK 2
BKPT 10+ (BKPT ack) 68010+

System / privileged

Mnemonic Best case Notes
ILLEGAL 14
RESET 521 68040 external reset timing
RTE (see Program control) 13-23 by stack format
STOP 1 (then idle)
ANDI ORI EORI to SR/CCR 8 (1L+7) 68000-compatible
MOVE to/from SR 3 (1L+2) / 5 (1L+4)
MOVE to/from CCR 3
MOVE USP 3 68010+
MOVEC 4 (1L+3) 68010+
MOVES 7 (1L+6) 68010+
MOVEM (reg→mem) 4+1/n (best) 12+4n for mem→reg on 68000; on 68040: 4-9 cycles
MOVEP 4-8 (word/long) supported by MC68040; MC68060 treats MOVEP as an unimplemented integer instruction
TAS (reg) 1 68000 atomic on 68040 too (locked transfer)
TAS (mem) 4+ with locked bus transfer
BKPT 10+ 68010+

Atomic (68020+)

Mnemonic Best case Notes
CAS (aligned) 1-3 atomic; 1 in cache, 3 with bus locked transfer
CAS2 5-7 supported on MC68020/MC68030/MC68040; unimplemented and software-handled on MC68060
CHK2 / CMP2 varies range-check/compare instructions introduced with MC68020

MMU (68030 PMMU, 68040 internal MMU)

Mnemonic Best case Notes
PFLUSH (An) 11 (1L+10) flush one entry
PFLUSHA 11 (1L+10) flush all ATC entries
PFLUSHAN 27 (1L+26) flush all + invalidate
PFLUSHN (An) 11 (1L+10) flush one, no invalidate
PTESTR PTESTW 25 (11L+14) 3-level table search, no descriptor writes, 4-clock memory

Cache (68040+)

Mnemonic Best case Notes
CINV 4-12 (per line) invalidate cache line(s)
CPUSH 4-12 (per line) push + invalidate

MOVE16 (68040+)

Mnemonic Best case Notes
MOVE16 (An)+ → (An)+ 8 (1L+7) first; +8 per successive line-aligned burst transfer
MOVE16 (An)+ → (xxx).L 8 (1L+7)
MOVE16 (xxx).L → (An)+ 8 (1L+7)
MOVE16 (cache hit) 11-8=3 per line (1L+2) both source/dest in cache

Floating-point (68882-instruction-set on integrated FPU)

Per MC68040UM §10.7, the integrated FPU can overlap execution with the integer unit subject to resource and memory-access constraints. The hardware timing rows below apply only to operations implemented by the MC68040 FPU. Rows for operations listed by Table 9-10 as unimplemented are retained so the section remains complete, but their timing cells are marked software-dependent because they are not native MC68040 FPU execution timings:

FPU operation Reg-Reg (W) Reg-Reg (D) Reg-Reg (X) Reg-Mem Mem-Reg
FADD FSUB 4 4 5 8 8
FMUL 4 5 6 9 9
FDIV 24 38 56 32 32
FSQRT 56 56 80 64 64
FABS FNEG FTST FCMP 2 2 3 6 6
FMOVE.X 2 2 2 4 (mem read) 4 (mem write)
FMOVE.P (packed-decimal handling may require FPSP) software-dependent software-dependent software-dependent software-dependent software-dependent
FINT FINTRZ (unimplemented in 68040 hardware) software-dependent software-dependent software-dependent software-dependent software-dependent
FMOVECR (unimplemented in 68040 hardware) software-dependent software-dependent software-dependent — —
FSIN FCOS FTAN (unimplemented in 68040 hardware) software-dependent software-dependent software-dependent software-dependent software-dependent
FSINCOS (unimplemented in 68040 hardware) software-dependent software-dependent software-dependent software-dependent software-dependent
FLOG10 FLOG2 FLOGN (unimplemented in 68040 hardware) software-dependent software-dependent software-dependent software-dependent software-dependent
FLOGNP1 (unimplemented in 68040 hardware) software-dependent software-dependent software-dependent software-dependent software-dependent
FETOX (unimplemented in 68040 hardware) software-dependent software-dependent software-dependent software-dependent software-dependent
FETOXM1 (unimplemented in 68040 hardware) software-dependent software-dependent software-dependent software-dependent software-dependent
FTENTOX FTWOTOX (unimplemented in 68040 hardware) software-dependent software-dependent software-dependent software-dependent software-dependent
FMOD FREM (unimplemented in 68040 hardware) software-dependent software-dependent software-dependent software-dependent software-dependent
FSAVE 22 22 22 22 —
FRESTORE 25 25 25 — 25
FBcc (taken) 10 10 10 10 10
FBcc (not taken) 8 8 8 8 8
FDBcc varies varies varies varies varies
FScc (false) 1 1 1 6 6
FScc (true) 1 1 1 6 6
FTRAPcc (taken) 10 10 10 10 10
FTRAPcc (not taken) 8 8 8 8 8
FNOP 8 8 8 8 8
FMOVEM 8 (1L+7) + 1 per reg first move + 1 per reg up to 16 regs

The MC68040 FPU executes its implemented arithmetic and conditional floating-point subset in hardware. Table 9-10 lists FINT, FINTRZ, FGETEXP, FGETMAN, FMOD, FREM, FSCALE, FMOVECR, and the transcendental operations as unimplemented; their execution time therefore depends on the installed AmigaOS CPU-support software, typically 68040.library. FDBcc, FScc, and FTRAPcc are implemented MC68040 conditional operations and must not be grouped with the software-handled instructions. The MC68060 has a different hardware/software split, handled on AmigaOS by 68060.library.

68040 summary: why it's fast

The 68040's dramatic speedup over 68020/68030 comes from three things: 1. 6-stage pipeline — single-cycle issue for most register-register ops 2. Branch cache — correctly predicted branches are 1 cycle (zero branch penalty on hit) 3. Integrated FPU + MMU — removes external-coprocessor/MMU overhead and permits substantial concurrent internal activity; exact overlap depends on instruction and memory-resource use

The key distinction is latency versus throughput. On the MC68000/MC68010, even simple register-register ALU operations commonly take multiple clocks (for example, a basic ADD is 4 clocks plus any applicable effective-address cost). The MC68020/MC68030 improve execution and memory behavior but are still single-issue designs. The MC68040 pipeline can sustain approximately one simple integer instruction per clock once filled under favorable conditions, while the MC68060 can issue two compatible integer instructions in one clock when the pOEP/sOEP pairing rules and dependencies permit it.

Accordingly, do not interpret individual best-case timing-table entries as whole-program IPC figures. Actual throughput depends on instruction mix, dependencies, cache behavior, branch prediction, effective-address calculation, and memory latency.

68060 base cycle counts (per MC68060UM Section 10)

Mnemonic Best case (regs) Long/word variants Notes
ADD AND OR EOR SUB SUBI ADDI ANDI ORI EORI 1 cycle same for all sizes Dn+Dn = 1(0/0)
ADDQ SUBQ 1 cycle same register-to-register
ADDA SUBA CMPA MOVEA 1 cycle same
CMP CMPI CMPA 1 cycle same
MOVE 1 cycle (1(0/0) for reg-to-reg) MOVE.L with memory adds 0-1 cycles
MOVEQ 1 cycle
MULS.W MULU.W 2 cycles (1(1/0)) word multiply
MULS.L MULU.L 2 cycles (1(1/0)) long multiply (non-wide)
MULS.L wide MULU.L wide software-dependent emulated on 68060 64-bit result; vector-61 software path
DIVS.W DIVU.W ≤22 cycles (variable) 1(1/0) base + variable word divide, conditional
DIVS.L DIVU.L 38 cycles (1(1/0) base + 37) long divide (non-wide)
DIVSL.L DIVUL.L hardware timing per MC68060UM native 32÷32 quotient/remainder forms are implemented in hardware
NEG NOT NEGX 1 cycle 1(0/0) for reg
CLR 1 cycle 1(0/0) for reg
TST 1 cycle 1(0/0) for reg
EXT.W EXT.L 1 cycle
EXTB.L 1 cycle 68020+
SWAP 1 cycle
ASL ASR LSL LSR 1+3n (n=shift count) up to 8 cycles for register shift
ROL ROR ROXL ROXR 1+3n up to 8 cycles
BCHG BCLR BSET BTST (register) 1-3 cycles memory destination adds
Bcc (predicted) 1 cycle (dual-issue)
Bcc (not predicted) 3-5 cycles
BRA BSR 3-4 cycles
JMP (An) 1 cycle
JSR (An) 3 cycles
RTS 4 cycles
RTR 7 cycles
JSR (d16,An) 4 cycles
LEA (An) 1 cycle
LEA (d16,An) 2 cycles
PEA (An) 2 cycles
LINK 4 cycles
UNLK 3 cycles
NOP 1 cycle
TRAP #n 14 cycles
STOP varies
RTE 8 cycles
RESET 519 cycles
MOVE16 18 cycles (1(1/1)) for line transfer; 11(1/1) if read hits cache
TAS 1 cycle (reg) / 17 cycles (memory)
CHK 8+ cycles (trap if out of bounds) hardware instruction
CHK2 software-dependent unimplemented on 68060; vector-61 software path
TRAPcc TRAPV 5+ cycles native on 68060 (1(0/0) per Table 10-24; trap handling adds cycles when taken)
BCHG BSET BCLR (memory) 4-7 cycles
BFCHG BFCLR BFSET BFTST 4-7 cycles 68020+ bit-field
BFEXTS BFEXTU BFINS BFFFO 4-7 cycles 68020+
PACK UNPK 4-7 cycles native on 68060 (2(0/0) register / 2(1/1) memory per Table 10-24)
CMP2 software-dependent emulated on 68060 vector-61 software path
CAS 19 cycles (1(1/1)) 68020+
CAS2 emulated on 68060 native on 68020/68030/68040; software-handled on 68060
MOVEM 3-12 cycles depending on count
MOVEC 6+ cycles 68010+ supervisor
MOVES 8+ cycles 68010+ supervisor
MOVE from SR 3 cycles (1(0/0)) 68000 unprivileged; 68010+ privileged
MOVE to SR 4 cycles (1(0/0)) supervisor
MOVE to CCR 4 cycles (1(0/0))
MOVE from CCR 3 cycles (1(0/0))
MOVE USP 3 cycles supervisor
ANDI ORI EORI to SR/CCR 8-10 cycles SR forms are privileged; CCR forms are not generically supervisor-only
BKPT 10+ cycles (BKPT ack)
CINV CPUSH 4+ cycles per line 68040+
PFLUSH see MC68060UM Table 10-24 / §4.7.2 native ATC operation on full MC68060/MC68LC060; the MC68EC060 no-MMU variant has separate no-op/illegal semantics
PLPA 4+ cycles 68060 only

Cycle counts for 68060 in this table are derived from MC68060UM Section 10.2 (Timing Assumptions: all instructions and data reside in the operand cache, no bus errors, no MMU translation, ICache hit). They are the base cycles that must be added to the effective-address calculation times of Table 10-5 (typically 0-3 cycles depending on the addressing mode). The 68060 uses dynamic branch prediction; correctly predicted branches are 1 cycle (dual-issue with the next instruction), mispredicted branches are 8-9 cycles.

68881/68882 FPU cycle counts (per MC68881/MC68882 datasheets)

The FPU cycle counts depend on the data format, source/destination type, and operation. Typical values:

FPU operation 68881 (typical cycles) 68882 (typical cycles, ~1.5×)
FADD.S FADD.D FADD.X (reg, reg) 4 / 4 / 6 3 / 3 / 4
FSUB.S FSUB.D FSUB.X 4 / 4 / 6 3 / 3 / 4
FMUL.S FMUL.D FMUL.X 7 / 8 / 10 4 / 5 / 6
FDIV.S FDIV.D FDIV.X 36 / 70 / 102 24 / 47 / 68
FSQRT.S FSQRT.D FSQRT.X 70 / 70 / 102 47 / 47 / 68
FABS FNEG 3 2
FTST 3 2
FCMP 3 / 3 / 5 2 / 2 / 3
FMOVE.X <ea>,FPn 3 (reg) / 4 (mem) 2 / 3
FMOVE.P 12 8
FINT FINTRZ 55 (FPn→FPm, 68881); 82/74/80/78/892 for Int/S/D/X/P per Table 8-2 58 Total (68882 FPn→FPm) per Table 8-3
FMOVECR 29 (FPn→FPm, 68881; no memory operand) per Table 8-2 32 Total (68882 FPn→FPm) per Table 8-3
FSIN FCOS FSQRT (68881/68882 transcendentals) 391 / 391 / 107 (68881 FPn→FPm); 1228 / 1228 / 944 Packed per Table 8-2 394 / 394 / 110 Total (68882 FPn→FPm) per Table 8-3
FLOG2 FLOG10 FLOGN (68881/68882) 581 / 581 / 525 (68881 FPn→FPm); 1418 / 1418 / 1352 Packed per Table 8-2 584 / 584 / 528 Total (68882 FPn→FPm) per Table 8-3
FSAVE / FRESTORE 22 / 25 14 / 17

For the full per-format tables see MC68881 Technical Summary (alldatasheet 1985) and MC68882 Technical Summary (alldatasheet 1990), both in the wiki archive.

Notes on semantics

  • MOVE from SR — On the 68000 it is unprivileged. On the 68010 and later, it is privileged. The 68010 introduced MOVE from CCR so user-mode software could read the condition-code byte without reading the full status register.
  • RTE — Stack frame format differs between 68000 and 68010+. The 68010 added a throwaway frame and a bus-cycle restart frame for virtual memory support; the format word on the stack tells the handler which kind is present.
  • TAS — A memory form uses the processor's read-modify-write mechanism and is intended as an atomic synchronization primitive. Whether that is sufficient for a particular multiprocessor system also depends on the platform's cache-coherency and bus design; do not state that cached TAS is inherently non-atomic on the 68040/68060.
  • CAS, CAS2, and TAS — Motorola classifies these as multiprocessor read-modify-write instructions that provide uninterrupted memory updates. Platform-specific coherency rules remain relevant, but the ISA operations themselves are atomic synchronization primitives.
  • MOVE16 — Transfers an aligned 16-byte block and is available on the MC68040 and MC68060. The architecture provides register-postincrement forms and absolute-long forms; use the exact operand restrictions and alignment rules from the target processor manual. Do not generalize misalignment behavior or cache-mode requirements from one implementation to the other without checking the specific 68040/68060 definition.
  • PFLUSH/PTEST — on full MC68060/MC68LC060, the PFLUSH family is native and operates on the on-die ATCs; PTEST is unimplemented. PLPA supplies the 68060-specific logical-to-physical translation helper. MC68EC060 has no MMU and must be treated separately.
  • MMU interface differences — The 68030 uses PMOVE to manipulate its MMU; the 68040 uses MOVEC plus PFLUSH/PTEST. Code that targets the 68030's MMU must be ported.

See also

Sources: Motorola, M68000 8-/16-/32-Bit Microprocessor User's Manual (MC68000UM), 1st printing 1992, Table 2-2 "Instruction Set Summary" (Sheets 1-4, pp. 2-11 → 2-14). Motorola, M68020 32-Bit Microprocessor User's Manual (MC68020UM), 1989, Table 1-2 "Instruction Set" (pp. 1-10 → 1-11); Chapter 1.4 "Instruction Set Overview"; Section 1.3 "Virtual Memory/Machine Concepts". Motorola, MC68030 User's Manual (MC68030UM), 1989/1990, Table 1-2 "Instruction Set" (pp. 1-12 → 1-13); Section 1.7 "The Memory Management Unit"; Section 1.9 "The Cache Memories". Motorola/Freescale, MC68040 User's Manual (MC68040UM), 1993, Table 1-4 "Instruction Set Summary" (pp. 1-14 → 1-21) and the FPU instruction list on p. 1-16. Motorola/Freescale, M68060 User's Manual (MC68060UM), 1993, Table 1-3 "Instruction Set Summary" (pp. 1-16 → 1-21); Appendix C.2 "Unimplemented Integer Instructions" (p. C-4); Section 6.5.1 "Unimplemented Floating-Point Instructions" Table 6-11 (p. 6-19). Motorola, M68000 Family Reference Manual — MC68881 Floating-Point Coprocessor section (extracted from the FRM as inbox/mtgf88xv_MC68881UM.PDF, 48-page scan, 1985); the file is image-only (no text layer), so I OCR'd it with tesseract 5.5.3 (nix-store binary) at 200 dpi via pdftoppm — extracted to raw/hardware/mc68881um.md for the 68881 chapter; cross-referenced with the publicly documented MC68881 instruction set and with MC68040UM Table 1-4 (which lists the full 68882 instruction set). Motorola, MC68881/MC68882 Floating-Point Coprocessor User's Manual / M68000 Family floating-point reference material; the local archive also contains OCR extracts of the MC68881 and MC68882 chapters. The two coprocessors share the same programmer-visible instruction set; the MC68882 primarily changes implementation/performance characteristics. 68010 deltas cross-referenced against MC68010UM (image-only PDF, content verified against publicly documented 68010 enhancements). Raw: raw/hardware/mc68000um.md (text extract via pdftotext from MC68000UM 188pp); raw/hardware/mc68020um.md (text extract via pdftotext from MC68020UM 452pp); raw/hardware/mc68030um.md (text extract via pdftotext from MC68030UM 599pp); raw/hardware/mc68040um.md (text extract via pdftotext from MC68040UM 442pp); raw/hardware/mc68060um.md (text extract via pdftotext from MC68060UM 416pp); raw/hardware/mc68881um.md (OCR via tesseract 5.5.3 from inbox/mtgf88xv_MC68881UM.PDF 48 pp scan at 200 dpi); raw/hardware/mc68882um.md (OCR via tesseract 5.5.3 from inbox/mtgfi0ge_MC68882UM.PDF 45 pp scan at 200 dpi). Updated: 2026-09-02